Progress with T2080 port refresh

dgarske · dgarske · commit ec28be7e49b1 · 2026-02-17T16:43:54.000-08:00
diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h
@@ -118,16 +118,17 @@
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
 
-    #define L2SRAM_ADDR   (0xF8F00000UL) /* CPC as SRAM (1MB) */
-    #define L2SRAM_SIZE   (1024UL * 1024UL)
+    /* T2080 CPC SRAM config - 512KB per T2080RM */
+    #define L2SRAM_ADDR   (0xF8F80000UL) /* CPC as SRAM (512KB) */
+    #define L2SRAM_SIZE   (512UL * 1024UL)
 
     #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
     /* CPC SRAM transactions traverse the CoreNet interconnect, which
-     * requires a LAW to route them. LAW_TRGT_DDR_1 is used as a routing
-     * target; the CPC intercepts the transaction before it reaches DDR. */
-    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_1MB
+     * requires a LAW to route them. LAW_TRGT_DDR_1 (0x10) is the CPC
+     * target per T2080RM Table 2-2 (Target ID Assignments). */
+    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_512KB
     #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
-    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M
+    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_512K
 
     #define ENABLE_INTERRUPTS
 
@@ -303,6 +304,7 @@
     #ifdef CORE_E6500
         /* T2080: 2MB CPC, 16 ways, 128KB per way */
         #define CPCSRCR0_SRAMSZ_256  (0x1 << 1) /* ways 14-15, 256KB */
+        #define CPCSRCR0_SRAMSZ_512  (0x2 << 1) /* ways 12-15, 512KB */
         #define CPCSRCR0_SRAMSZ_1024 (0x3 << 1) /* ways 8-15, 1MB */
         #define CPCSRCR0_SRAMSZ_2048 (0x4 << 1) /* ways 0-15, 2MB */
     #else /* CORE E5500 */
@@ -691,12 +693,12 @@ extern void dcache_disable(void);
 #else
 /* Assembly version */
 #ifdef CORE_E6500
-/* e6500 has 64-bit MAS registers - must clear upper 32 bits.
- * Using lis would sign-extend values with bit 15 set (e.g., 0xC000xxxx).
- * Use li 0; oris; ori pattern for all MAS registers. */
+/* e6500 has 64-bit MAS registers. On 64-bit PPC, lis sign-extends to 64 bits.
+ * Any MAS value with bit 31 set (MAS1=0xC..., MAS2/MAS3 high addresses) gets
+ * upper 32 bits = 0xFFFFFFFF. Hardware may require reserved upper bits = 0.
+ * Use "li 0; oris; ori" pattern for MAS1, MAS2, MAS3 to avoid sign-extension. */
 #define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
-    li    reg, 0; \
-    oris  reg, reg, BOOKE_MAS0(tlb, esel, 0)@h; \
+    lis   reg, BOOKE_MAS0(tlb, esel, 0)@h; \
     ori   reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
     mtspr MAS0, reg;\
     li    reg, 0; \
diff --git a/hal/nxp_t2080.c b/hal/nxp_t2080.c
@@ -221,7 +221,7 @@ static void hal_flash_init(void)
 #endif /* ENABLE_IFC */
 }
 
-static void hal_ddr_init(void)
+void hal_ddr_init(void)
 {
 #ifdef ENABLE_DDR
     uint32_t reg;
@@ -358,8 +358,8 @@ static void hal_cpld_init(void)
     set32(IFC_AMASK(3), IFC_AMASK_64KB);
     set32(IFC_CSOR(3), 0);
 
-    /* IFC - CPLD */
-    set_law(2, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
+    /* IFC - CPLD (use LAW 5; LAW 2 is used for CPC SRAM) */
+    set_law(5, CPLD_BASE_PHYS_HIGH, CPLD_BASE,
         LAW_TRGT_IFC, LAW_SIZE_4KB, 1);
 
     /* CPLD - TBL=1, Entry 17 */
diff --git a/hal/nxp_t2080.ld b/hal/nxp_t2080.ld
@@ -13,8 +13,9 @@ MEMORY
 {
     FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
 
-    /* CPC as SRAM - 1MB */
-    RAM (rwx) : ORIGIN = 0xF8F00000, LENGTH = 0x100000
+    /* CPC as SRAM - 512KB (T2080 supports up to 2MB, using 512KB)
+     * Layout: .ramcode at bottom, stack grows down from top */
+    RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x80000
 
     /* DDR - 2GB */
     DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF
@@ -57,7 +58,21 @@ SECTIONS
     .gnu.hash       : { *(.gnu.hash) }
     .rela.dyn       : { *(.rela.dyn) }
 
-    _stored_data = .;
+    /* Store flash location for .ramcode copy */
+    _stored_ramcode = .;
+
+    /* RAMFUNCTION code in CPC SRAM - copied before DDR is used
+     * This ensures memcpy/memmove are available early */
+    .ramcode : AT (_stored_ramcode)
+    {
+        _start_ramcode = .;
+        KEEP(*(.ramcode))
+        . = ALIGN(4);
+        _end_ramcode = .;
+    } > RAM
+
+    /* Calculate where .data starts in flash (after .ramcode) */
+    _stored_data = _stored_ramcode + (_end_ramcode - _start_ramcode);
 
     .data : AT (_stored_data)
     {
@@ -68,8 +83,6 @@ SECTIONS
         *(.plt*)
         *(.dynamic)
         . = ALIGN(4);
-        KEEP(*(.ramcode))
-        . = ALIGN(4);
         _end_data = .;
     } > DRAM
 
@@ -88,5 +101,7 @@ SECTIONS
 
 }
 
-PROVIDE(_start_heap = ORIGIN(RAM));
+/* Heap starts after .ramcode in CPC SRAM */
+PROVIDE(_start_heap = _end_ramcode);
+/* Stack at top of CPC SRAM, grows down */
 PROVIDE(_end_stack  = ORIGIN(RAM) + (LENGTH(RAM)) );
diff --git a/src/boot_ppc.c b/src/boot_ppc.c
@@ -31,6 +31,10 @@ extern unsigned int __bss_end__;
 extern unsigned int _stored_data;
 extern unsigned int _start_data;
 extern unsigned int _end_data;
+/* .ramcode section (RAMFUNCTION) - may be in separate memory region */
+extern unsigned int _stored_ramcode;
+extern unsigned int _start_ramcode;
+extern unsigned int _end_ramcode;
 
 extern void main(void);
 extern void hal_early_init(void);
@@ -124,12 +128,33 @@ void boot_entry_C(void)
     volatile const unsigned int *src;
     volatile unsigned int *end;
 
+    /* Copy .ramcode section FIRST - to CPC SRAM which is already available.
+     * This makes RAMFUNCTION code (memcpy, memmove) available before DDR.
+     * Use volatile to prevent compiler from transforming to memcpy call. */
+    src = (volatile const unsigned int*)&_stored_ramcode;
+    dst = (volatile unsigned int*)&_start_ramcode;
+    end = (volatile unsigned int*)&_end_ramcode;
+    while (dst < end) {
+        *dst = *src;
+        dst++;
+        src++;
+    }
+
+#ifndef BUILD_LOADER_STAGE1
+    /* Flush D-cache and invalidate I-cache for .ramcode in CPC SRAM.
+     * PowerPC I/D caches are not coherent — explicit dcbst+icbi required. */
+    if ((uint32_t)&_end_ramcode > (uint32_t)&_start_ramcode) {
+        flush_cache((uint32_t)&_start_ramcode,
+            (uint32_t)&_end_ramcode - (uint32_t)&_start_ramcode);
+    }
+#endif
+
+    /* Now initialize DDR and other hardware */
     hal_early_init();
 
-    /* Copy the .data section from flash to RAM.
+    /* Copy the .data section from flash to DDR.
      * Use volatile to prevent the compiler from transforming this loop
-     * into a memcpy() call — memcpy is RAMFUNCTION in .data and hasn't
-     * been copied to DDR yet at this point. */
+     * into a memcpy() call. */
     src = (volatile const unsigned int*)&_stored_data;
     dst = (volatile unsigned int*)&_start_data;
     end = (volatile unsigned int*)&_end_data;
@@ -140,12 +165,7 @@ void boot_entry_C(void)
     }
 
 #ifndef BUILD_LOADER_STAGE1
-    /* Flush D-cache and invalidate I-cache for .data region.
-     * The .ramcode section (RAMFUNCTION code like memcpy) is within .data
-     * and was just copied to DDR through D-cache. Without this flush, the
-     * I-cache will fetch stale/uninitialized DDR content when calling
-     * RAMFUNCTION code, causing instruction fetch failures.
-     * PowerPC I/D caches are not coherent — explicit dcbst+icbi required. */
+    /* Flush D-cache and invalidate I-cache for .data region in DDR. */
     flush_cache((uint32_t)&_start_data,
         (uint32_t)&_end_data - (uint32_t)&_start_data);
 #endif
diff --git a/src/boot_ppc_start.S b/src/boot_ppc_start.S
@@ -560,70 +560,116 @@ flash_tlb:
     #endif
 #endif /* ENABLE_DDR */
 
+/* =========================================================================
+ * CPC SRAM Initialization
+ * Order: 1) CPC invalidate, 2) CPCSRCR config, 3) LAW, 4) TLB, 5) CPC enable
+ * Note: TLB must be created BEFORE CPC enable (original working sequence)
+ * ========================================================================= */
+#if defined(ENABLE_L2_CACHE) && defined(L2SRAM_ADDR) && (defined(CORE_E5500) || defined(CORE_E6500))
+cpc_setup_sram:
+        /* T2080RM: 8.4.2.2 - CPC initialization sequence:
+         * Step 1: Flash invalidate CPC and clear locks (CPCFI | CPCLFC)
+         * Step 2: Poll until invalidate completes
+         * Step 3: Configure SRAM control registers (CPCSRCR1, CPCSRCR0)
+         * Step 4: Configure LAW for SRAM routing (done after this block)
+         * Step 5: Enable CPC with parity (CPCE | CPCPE)
+         * Step 6: Create TLB for SRAM access
+         * The LAW (DDR_1) provides CoreNet routing; CPC intercepts before DDR. */
+
+        /* R1 = CPC base - preserve across LAW setup */
+        LOAD_ADDR32(r1, CPC_BASE)
+
+        /* Step 1: Flash invalidate CPC and clear all locks */
+        lis     r0, (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)@h
+        ori     r0, r0, (CPCCSR0_CPCFI | CPCCSR0_CPCLFC)@l
+        stw     r0, CPCCSR0(r1)
+
+        /* Step 2: Poll until CPCFI and CPCLFC clear */
+cpc_poll_invalidate:
+        lwz     r2, CPCCSR0(r1)
+        and.    r2, r2, r0
+        bne     cpc_poll_invalidate
+        isync
+
+        /* Step 3: Configure CPC SRAM control registers */
+        li      r0, 0
+        stw     r0, CPCSRCR1(r1) /* SRAM high address = 0 */
+        /* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
+        LOAD_ADDR32(r0, L2SRAM_ADDR)
+        /* Enable SRAM and set size (must match L2SRAM_SIZE = 512KB) */
+        ori     r0, r0, (CPCSRCR0_SRAMSZ_512 | CPCSRCR0_SRAMEN)
+        stw     r0, CPCSRCR0(r1)
+        mbar
+        isync
+#endif /* ENABLE_L2_CACHE && L2SRAM_ADDR */
+
+/* Step 3: Configure LAW for SRAM */
 #ifdef INITIAL_SRAM_ADDR
 #ifndef INITIAL_SRAM_NO_LAW
 init_sram_law:
-        /* Intial SRAM LAW 2 */
+        /* CPC SRAM uses LAW 2 - DO NOT reuse this LAW index elsewhere!
+         * The stack resides in CPC SRAM; overwriting this LAW causes crashes. */
         #define INITIAL_SRAM_LAW (LAWAR_ENABLE | \
                                   LAWAR_TRGT_ID(INITIAL_SRAM_LAW_TRGT) | \
                                   INITIAL_SRAM_LAW_SZ)
         LOAD_ADDR32(r9, CCSRBAR + LAWBAR_BASE(2))
         li      r0,     0 /* UPPER=0 */
         /* Use LOAD_ADDR32 on e6500 to avoid sign-extension for addresses >= 0x80000000 */
-        LOAD_ADDR32(r1, INITIAL_SRAM_ADDR)
+        LOAD_ADDR32(r3, INITIAL_SRAM_ADDR)
         LOAD_ADDR32(r2, INITIAL_SRAM_LAW)
         stw     r0, 0(r9) /* LAWBARH */
-        stw     r1, 4(r9) /* LAWBARL */
+        stw     r3, 4(r9) /* LAWBARL */
         sync
         stw     r2, 8(r9) /* LAWAR */
         /* read back LAWAR (per 2.3.2 Configuring Local Access Windows) */
         lwz     r2, 8(r9)
         isync
 #endif /* !INITIAL_SRAM_NO_LAW */
+#endif /* INITIAL_SRAM_ADDR */
 
+/* Step 4: Create TLB for SRAM - BEFORE CPC enable (original working order)
+ * This is for e5500/e6500 CPC SRAM only. e500 has its own init_sram_tlb below. */
+#if defined(INITIAL_SRAM_ADDR) && (defined(CORE_E5500) || defined(CORE_E6500))
 init_sram_tlb:
         /* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT
-         * CPC SRAM uses cacheable memory-coherent (M) access.
-         * TLB is created BEFORE l2_setup_sram per old working code. */
+         * Original working T2080 code (commit 11f46a51) used MAS2_M. */
         set_tlb(1, 9,
                 INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0,
                 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
                 INITIAL_SRAM_BOOKE_SZ, 1, r3);
-#endif
-
-#ifdef ENABLE_L2_CACHE
+#endif /* INITIAL_SRAM_ADDR && (CORE_E5500 || CORE_E6500) */
 
-#if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */
-#ifdef L2SRAM_ADDR
-l2_setup_sram:
-        /* T2080RM: 8.4.2.2 - CPC initialization
-         * Configure SRAM control registers, then enable CPC with parity.
-         * The LAW (DDR_1) provides CoreNet routing; CPC intercepts before DDR.
-         * SRAM is zeroed later via dcbz through cacheable TLB (MAS2_M). */
+/* Step 5: Enable CPC after TLB is configured */
+#if defined(ENABLE_L2_CACHE) && defined(L2SRAM_ADDR) && (defined(CORE_E5500) || defined(CORE_E6500))
+cpc_enable:
         /* R1 = CPC base */
         LOAD_ADDR32(r1, CPC_BASE)
 
-        /* Configure CPC SRAM control registers */
-        li      r0, 0
-        stw     r0, CPCSRCR1(r1) /* SRAM high address = 0 */
-        /* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
-        LOAD_ADDR32(r0, L2SRAM_ADDR)
-        /* Enable SRAM and set size (must match L2SRAM_SIZE) */
-        ori     r0, r0, (CPCSRCR0_SRAMSZ_1024 | CPCSRCR0_SRAMEN)
-        stw     r0, CPCSRCR0(r1)
-
         /* Enable CPC with parity */
         lis     r0, (CPCCSR0_CPCE | CPCCSR0_CPCPE)@h
         mbar
         isync
         stw     r0, CPCCSR0(r1)
         mbar
 
+        /* Verify CPC is enabled by reading back CPCCSR0 */
+cpc_poll_enable:
+        lwz     r2, CPCCSR0(r1)
+        andis.  r2, r2, CPCCSR0_CPCE@h  /* check CPCE bit */
+        beq     cpc_poll_enable
+        isync
+
         /* Disable speculation (Errata A-006593) */
         lwz     r0, CPCHDBCR0(r1)
         oris    r0, r0, CPCHDBCR0_SPEC_DIS@h
         stw     r0, CPCHDBCR0(r1)
-#endif /* L2SRAM_ADDR */
+        mbar
+        isync
+#endif /* ENABLE_L2_CACHE && L2SRAM_ADDR */
+
+#ifdef ENABLE_L2_CACHE
+#if defined(CORE_E5500) || defined(CORE_E6500) /* --- L2 E5500/E6500 --- */
+/* Note: CPC SRAM setup moved above for correct T2080RM sequence */
 
 #if defined(CORE_E6500) /* --- L2 E6500 --- */
 l2_setup_cache:
@@ -653,6 +699,13 @@ l2_poll_invclear:
         isync
         LOAD_ADDR32(r4, (L2CSR0_L2E | L2CSR0_L2PE))
         stw     r4, L2CSR0(r5)
+        mbar
+
+        /* Verify L2 is enabled by reading back L2CSR0 */
+l2_poll_enable:
+        lwz     r3, L2CSR0(r5)
+        andis.  r3, r3, L2CSR0_L2E@h  /* check bit 31 (L2E) */
+        beq     l2_poll_enable        /* loop until enabled */
         isync
 
 #elif defined(CORE_E5500) /* --- L2 E5500 --- */
@@ -714,6 +767,17 @@ l2_setup_sram:
         stw     r1, L2SRBAR0(r5)
         mbar
 #endif /* L2SRAM_ADDR */
+
+#ifdef INITIAL_SRAM_ADDR
+init_sram_tlb:
+        /* Initial SRAM: TLB 1, Entry 9, Supervisor X/R/W, M, TS=0, IPROT
+         * For e500, L2 SRAM uses cacheable memory-coherent (M) access.
+         * TLB is created AFTER l2_setup_sram configures L2 as SRAM. */
+        set_tlb(1, 9,
+                INITIAL_SRAM_ADDR, INITIAL_SRAM_ADDR, 0,
+                MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
+                INITIAL_SRAM_BOOKE_SZ, 1, r3);
+#endif /* INITIAL_SRAM_ADDR */
 #endif /* CORE_E500 */
 #endif /* ENABLE_L2_CACHE */
 
@@ -776,9 +840,9 @@ cache_sram_init_loop:
         bdnz    cache_sram_init_loop
 #elif defined(L2SRAM_ADDR)
 cache_sram_init:
-        /* Zero CPC SRAM via cache (MAS2_M = cacheable, memory coherent).
-         * dcbz allocates zeroed cache lines without reading from CPC,
-         * avoiding ECC/parity issues from uninitialized SRAM. */
+        /* Zero CPC SRAM via dcbz.
+         * With MAS2_M (memory-coherent), dcbz allocates zeroed cache lines.
+         * This initializes SRAM and avoids ECC/parity issues from uninitialized data. */
         LOAD_ADDR32(r3, L2SRAM_ADDR)
         li      r0, 0
         LOAD_ADDR32(r2, (L2SRAM_SIZE / CACHE_LINE_SIZE))
