Port improvements

Author: dgarske

.github/workflows/test-configs.yml

@@ -182,12 +182,6 @@ jobs:
       arch: ppc
       config-file: ./config/examples/nxp-t1024.config
 
-  nxp_t2080_68ppc2_test:
-    uses: ./.github/workflows/test-build.yml
-    with:
-      arch: ppc
-      config-file: ./config/examples/nxp-t2080-68ppc2.config
-
   nxp_t2080_test:
     uses: ./.github/workflows/test-build.yml
     with:

arch.mk

@@ -627,15 +627,15 @@ endif
 ifeq ($(ARCH),PPC)
   CROSS_COMPILE?=powerpc-linux-gnu-
   LDFLAGS+=-Wl,--build-id=none
-  CFLAGS+=-DARCH_PPC -DFAST_MEMCPY
+  CFLAGS+=-DARCH_PPC -DFAST_MEMCPY -ffreestanding -fno-tree-loop-distribute-patterns
 
   ifeq ($(DEBUG_UART),0)
     CFLAGS+=-fno-builtin-printf
   endif
 
   # Target-specific CPU flags
   ifeq ($(TARGET),nxp_t2080)
-    CFLAGS+=-mcpu=e6500 -mno-altivec
+    CFLAGS+=-mcpu=e6500 -mno-altivec -mbss-plt
   else ifeq ($(TARGET),nxp_t1024)
     CFLAGS+=-mcpu=e5500
   endif

config/examples/nxp-t2080-68ppc2.config

@@ -1,8 +1,16 @@
+# NXP T2080 wolfBoot Configuration Template
+#
+# Stock (default): Compact layout, NOR base 0xEFFE0000
+# NAII 68PPC2 (alternate): Larger app partition, NOR base 0xE8000000
+#   Uncomment the "# NAII 68PPC2:" lines and comment the stock lines to use.
+
 ARCH=PPC
 TARGET=nxp_t2080
 SIGN?=ECC384
 HASH?=SHA384
+IMAGE_HEADER_SIZE?=512
 DEBUG?=0
+DEBUG_SYMBOLS?=1
 DEBUG_UART?=1
 VTOR?=1
 CORTEX_M0?=0
@@ -17,25 +25,43 @@ WOLFBOOT_VERSION?=0
 NO_MPU?=0
 SPMATH?=0
 SPMATHALL?=1
-RAM_CODE?=0
+RAM_CODE?=1
 DUALBANK_SWAP?=0
-PKA?=1
 WOLFTPM?=0
-WOLFBOOT_ORIGIN?=0xEFFE0000
-WOLFBOOT_PARTITION_SIZE?=0x20000
-WOLFBOOT_SECTOR_SIZE?=0x10000
 
+# NOR Base Address
 ARCH_FLASH_OFFSET?=0xEFFE0000
+# NAII 68PPC2: ARCH_FLASH_OFFSET?=0xE8000000
+
+# Flash Sector Size
+WOLFBOOT_SECTOR_SIZE?=0x10000
+
+# wolfBoot start address
+WOLFBOOT_ORIGIN?=0xEFFE0000
+# NAII 68PPC2: WOLFBOOT_ORIGIN?=0xEFF40000
+# wolfBoot partition size (custom)
 BOOTLOADER_PARTITION_SIZE=0x20000
 
+# Application Partition Size
+WOLFBOOT_PARTITION_SIZE?=0x20000
+# NAII 68PPC2: WOLFBOOT_PARTITION_SIZE?=0xA00000
+# Location in Flash for Application Partition
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFFC0000
+# NAII 68PPC2: WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xE8080000
+# Load Partition to RAM Address
 WOLFBOOT_LOAD_ADDRESS?=0x19000
+
+# Location in Flash for Update Partition
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFFA0000
+# NAII 68PPC2: WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xE8A80000
 
 # Location of temporary sector used during updates
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFF90000
+# NAII 68PPC2: WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xE8060000
 
 # DTS (Device Tree)
 WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
 WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
+# DTS Load to RAM Address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
+# NAII 68PPC2: WOLFBOOT_LOAD_DTS_ADDRESS?=0x40000

config/examples/nxp-t2080.config

@@ -3061,9 +3061,8 @@ Flash factory_custom.bin to NOR base 0xEC00_0000
 
 The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Support has been tested with the NAII 68PPC2.
 
-Example configurations for this target are provided in:
-* NXP T2080: [/config/examples/nxp-t2080.config](/config/examples/nxp-t2080.config).
-* NAII 68PPC2: [/config/examples/nxp-t2080-68ppc2.config](/config/examples/nxp-t2080-68ppc2.config).
+Example configuration: [/config/examples/nxp-t2080.config](/config/examples/nxp-t2080.config).
+Stock layout is default; for NAII 68PPC2, uncomment the "# NAII 68PPC2:" lines and comment the stock lines.
 
 ### Design NXP T2080 PPC
 
@@ -3080,9 +3079,10 @@ RM 4.3.3 Boot Space Translation
 By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`).
 
 The `make` creates a `factory.bin` image that can be programmed at `0xE8080000`
+(For NAII 68PPC2, first edit `nxp-t2080.config` to uncomment the NAII 68PPC2 lines.)
 
 ```
-cp ./config/examples/nxp-t2080-68ppc2.config .config
+cp ./config/examples/nxp-t2080.config .config
 make clean
 make keytools
 make

docs/Targets.md

@@ -133,7 +133,7 @@
 
     #define ENABLE_DDR
     #ifndef DDR_SIZE
-    #define DDR_SIZE (8192UL * 1024UL * 1024UL)
+    #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL)
     #endif
 
     #define FLASH_BASE_ADDR      0xE8000000UL

hal/nxp_ppc.h

@@ -200,38 +200,24 @@ static int hal_flash_getid(void)
 static void hal_flash_init(void)
 {
 #ifdef ENABLE_IFC
-    /* IFC - NOR Flash */
-    /* LAW is also set in boot_ppc_start.S:flash_law */
-    set_law(1, FLASH_BASE_PHYS_HIGH, FLASH_BASE_ADDR, LAW_TRGT_IFC, LAW_SIZE_128MB, 1);
-
-    /* NOR IFC Flash Timing Parameters */
-    set32(IFC_FTIM0(0), (IFC_FTIM0_NOR_TACSE(4) |
-                         IFC_FTIM0_NOR_TEADC(5) |
-                         IFC_FTIM0_NOR_TEAHC(5)));
-    set32(IFC_FTIM1(0), (IFC_FTIM1_NOR_TACO(53) |
-                         IFC_FTIM1_NOR_TRAD(26) |
-                         IFC_FTIM1_NOR_TSEQ(19)));
-    set32(IFC_FTIM2(0), (IFC_FTIM2_NOR_TCS(4) |
-                         IFC_FTIM2_NOR_TCH(4) |
-                         IFC_FTIM2_NOR_TWPH(14) |
-                         IFC_FTIM2_NOR_TWP(28)));
-    set32(IFC_FTIM3(0), 0);
-    /* NOR IFC Definitions (CS0) */
-    set32(IFC_CSPR_EXT(0), FLASH_BASE_PHYS_HIGH);
-    set32(IFC_CSPR(0),     (IFC_CSPR_PHYS_ADDR(FLASH_BASE_ADDR) |
-                        #if FLASH_CFI_WIDTH == 16
-                            IFC_CSPR_PORT_SIZE_16 |
-                        #else
-                            IFC_CSPR_PORT_SIZE_8 |
-                        #endif
-                            IFC_CSPR_MSEL_NOR |
-                            IFC_CSPR_V));
-    set32(IFC_AMASK(0), IFC_AMASK_128MB);
-    set32(IFC_CSOR(0), 0x0000000C); /* TRHZ (80 clocks for read enable high) */
+    /* IFC CS0 - NOR Flash
+     * Do NOT reprogram IFC CS0 (CSPR, AMASK, CSOR, FTIM) while executing
+     * from flash (XIP) with cache-inhibited TLB (MAS2_I|MAS2_G). The boot
+     * ROM already configured CS0 correctly. Reprogramming CSPR while XIP
+     * can cause instruction fetch failures because there is no cache to
+     * serve fetches during the chip-select decode transition.
+     *
+     * U-Boot avoids this by using MAS2_W|MAS2_G (write-through, cached)
+     * during XIP, only switching to MAS2_I|MAS2_G after relocating to RAM.
+     *
+     * The LAW is also already set in boot_ppc_start.S:flash_law.
+     */
 
-    #ifndef BUILD_LOADER_STAGE1
-    hal_flash_getid();
-    #endif
+    /* Note: hal_flash_getid() is disabled because AMD Autoselect mode
+     * affects the entire flash bank. Since wolfBoot runs XIP from the same
+     * bank (CS0), entering Autoselect mode crashes instruction fetch.
+     * Flash write/erase operations will need RAMFUNCTION support.
+     * TODO: Implement RAMFUNCTION for flash operations on T2080. */
 #endif /* ENABLE_IFC */
 }
 
@@ -578,7 +564,7 @@ void hal_flash_lock(void)
 /* from boot_ppc_mp.S */
 extern uint32_t _secondary_start_page;
 extern uint32_t _second_half_boot_page;
-extern uint32_t _spin_table;
+extern uint32_t _spin_table[];
 extern uint32_t _spin_table_addr;
 extern uint32_t _bootpg_addr;
 
@@ -593,7 +579,7 @@ static void hal_mp_up(uint32_t bootpg)
     active_cores = (1 << whoami); /* current running cores */
 
     wolfBoot_printf("MP: Starting cores (boot page %p, spin table %p)\n",
-        bootpg, (uint32_t)&_spin_table);
+        bootpg, (uint32_t)_spin_table);
 
     /* Set the boot page translation register */
     set32(LCC_BSTRH, 0);
@@ -614,7 +600,7 @@ static void hal_mp_up(uint32_t bootpg)
     while (timeout) {
         for (i = 0; i < CPU_NUMCORES; i++) {
             uint32_t* entry = (uint32_t*)(
-                  (uint8_t*)&_spin_table + (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
+                  (uint8_t*)_spin_table + (i * ENTRY_SIZE) + ENTRY_ADDR_LOWER);
             if (*entry) {
                 active_cores |= (1 << i);
             }
@@ -651,14 +637,17 @@ static void hal_mp_init(void)
     const volatile uint32_t *s;
     volatile uint32_t *d;
 
-    /* Assign virtual boot page at end of DDR */
-    bootpg = DDR_ADDRESS + DDR_SIZE - BOOT_ROM_SIZE;
+    /* Assign virtual boot page at end of LAW-mapped DDR region.
+     * DDR LAW maps 2GB (LAW_SIZE_2GB) starting at DDR_ADDRESS.
+     * DDR_SIZE may exceed 32-bit range (e.g. 8GB), so use the LAW-mapped
+     * size to ensure bootpg fits in 32 bits and is accessible. */
+    bootpg = DDR_ADDRESS + 0x80000000UL - BOOT_ROM_SIZE;
 
     /* Store the boot page address for use by additional CPU cores */
     _bootpg_addr = (uint32_t)&_second_half_boot_page;
 
     /* Store location of spin table for other cores */
-    _spin_table_addr = (uint32_t)&_spin_table;
+    _spin_table_addr = (uint32_t)_spin_table;
 
     /* Flush bootpg before copying to invalidate any stale cache lines */
     flush_cache(bootpg, BOOT_ROM_SIZE);
@@ -748,7 +737,7 @@ int hal_dts_fixup(void* dts_addr)
     #ifdef ENABLE_MP
         /* calculate location of spin table for core */
         core_spin_table = (uint64_t)((uintptr_t)(
-                  (uint8_t*)&_spin_table + (core * ENTRY_SIZE)));
+                  (uint8_t*)_spin_table + (core * ENTRY_SIZE)));
 
         fdt_fixup_str(fdt, off, "cpu", "status", (core == 0) ? "okay" : "disabled");
         fdt_fixup_val64(fdt, off, "cpu", "cpu-release-addr", core_spin_table);

hal/nxp_t2080.c

@@ -63,6 +63,10 @@ SECTIONS
     {
         _start_data = .;
         KEEP(*(.data*))
+        *(.got*)
+        *(.got2*)
+        *(.plt*)
+        *(.dynamic)
         . = ALIGN(4);
         KEEP(*(.ramcode))
         . = ALIGN(4);

hal/nxp_t2080.ld

@@ -47,6 +47,8 @@ extern "C" {
 #  if defined(__WOLFBOOT) && defined(RAM_CODE)
 #    if defined(ARCH_ARM)
 #      define RAMFUNCTION __attribute__((used,section(".ramcode"),long_call))
+#    elif defined(ARCH_PPC)
+#      define RAMFUNCTION __attribute__((used,section(".ramcode"),longcall))
 #    else
 #      define RAMFUNCTION __attribute__((used,section(".ramcode")))
 #    endif

include/wolfboot/wolfboot.h

@@ -113,25 +113,46 @@ int WEAKFUNCTION hal_dts_fixup(void* dts_addr)
 }
 #endif
 
+/* forward declaration */
+#ifndef BUILD_LOADER_STAGE1
+void flush_cache(uint32_t start_addr, uint32_t size);
+#endif
+
 void boot_entry_C(void)
 {
-    register unsigned int *dst, *src, *end;
+    volatile unsigned int *dst;
+    volatile const unsigned int *src;
+    volatile unsigned int *end;
 
     hal_early_init();
 
-    /* Copy the .data section from flash to RAM */
-    src = (unsigned int*)&_stored_data;
-    dst = (unsigned int*)&_start_data;
-    end = (unsigned int*)&_end_data;
+    /* Copy the .data section from flash to RAM.
+     * Use volatile to prevent the compiler from transforming this loop
+     * into a memcpy() call — memcpy is RAMFUNCTION in .data and hasn't
+     * been copied to DDR yet at this point. */
+    src = (volatile const unsigned int*)&_stored_data;
+    dst = (volatile unsigned int*)&_start_data;
+    end = (volatile unsigned int*)&_end_data;
     while (dst < end) {
         *dst = *src;
         dst++;
         src++;
     }
 
-    /* Initialize the BSS section to 0 */
-    dst = (unsigned int*)&__bss_start__;
-    end = (unsigned int*)&__bss_end__;
+#ifndef BUILD_LOADER_STAGE1
+    /* Flush D-cache and invalidate I-cache for .data region.
+     * The .ramcode section (RAMFUNCTION code like memcpy) is within .data
+     * and was just copied to DDR through D-cache. Without this flush, the
+     * I-cache will fetch stale/uninitialized DDR content when calling
+     * RAMFUNCTION code, causing instruction fetch failures.
+     * PowerPC I/D caches are not coherent — explicit dcbst+icbi required. */
+    flush_cache((uint32_t)&_start_data,
+        (uint32_t)&_end_data - (uint32_t)&_start_data);
+#endif
+
+    /* Initialize the BSS section to 0 (volatile prevents memset transform) */
+    dst = (volatile unsigned int*)&__bss_start__;
+    end = (volatile unsigned int*)&__bss_end__;
     while (dst < end) {
         *dst = 0U;
         dst++;