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dgarskedgarske
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Progress with support for multiple T2080 vendor boards.
1 parent 99aba9d commit b59649a

3 files changed

Lines changed: 95 additions & 85 deletions

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‎config/examples/nxp-t2080.config‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,13 @@
1-
# NXP T2080 wolfBoot Configuration Template
1+
# NXP T2080 wolfBoot Configuration
2+
# Default board: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
3+
#
4+
# Board selection: uncomment exactly one line to override the default.
5+
# Default (no define): T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
6+
# BOARD_CW_VPX3152: CW VPX3-152 (66.667 MHz oscillator, DDR3L)
7+
# BOARD_NAII_68PPC2: NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
8+
#
9+
#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
10+
#CFLAGS_EXTRA+=-DBOARD_NAII_68PPC2
211

312
ARCH=PPC
413
TARGET=nxp_t2080

‎hal/nxp_ppc.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -139,10 +139,10 @@
139139

140140
#define ENABLE_DDR
141141
#ifndef DDR_SIZE
142-
#ifdef BOARD_VPX3152
142+
#ifdef BOARD_CW_VPX3152
143143
#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* TODO: confirm from CS_BNDS dump (4/8/16 GB) */
144144
#else
145-
#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* NAII 68PPC2: 8 GB */
145+
#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* T2080 RDB / NAII 68PPC2: 8 GB */
146146
#endif
147147
#endif
148148

@@ -161,8 +161,8 @@
161161
/* Flash base address and size — may differ between board variants.
162162
* TODO: Confirm VPX3-152 flash mapping from IFC CSPR(0)/AMASK(0) dump.
163163
* If the new board uses a different base address (e.g. 0xF0000000 for
164-
* 256 MB flash), update the BOARD_VPX3152 values and uncomment. */
165-
#if 0 && defined(BOARD_VPX3152)
164+
* 256 MB flash), update the BOARD_CW_VPX3152 values and uncomment. */
165+
#if 0 && defined(BOARD_CW_VPX3152)
166166
#define FLASH_BASE_ADDR 0xF0000000UL /* TODO: from IFC dump */
167167
#define FLASH_BASE_PHYS_HIGH 0x0ULL
168168
#define FLASH_LAW_SIZE LAW_SIZE_256MB

‎hal/nxp_t2080.h‎

Lines changed: 81 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,9 @@
1919
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
2020
*
2121
* Board support:
22-
* Default: NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
23-
* BOARD_VPX3152: CW VPX3-152 (66.667 MHz oscillator, DDR3L)
22+
* Default: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
23+
* BOARD_CW_VPX3152: CW VPX3-152 (66.667 MHz oscillator, DDR3L)
24+
* BOARD_NAII_68PPC2: NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
2425
*
2526
* NXP T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011
2627
*/
@@ -37,10 +38,10 @@
3738
* hal_get_plat_clk() / hal_get_bus_clk() compute the actual frequencies
3839
* from the CLOCKING registers (PLL ratio × SYS_CLK) when
3940
* ENABLE_BUS_CLK_CALC is defined. */
40-
#ifdef BOARD_VPX3152
41-
#define SYS_CLK (66666667) /* 66.667 MHz oscillator (CW VPX3-152) */
42-
#else
41+
#ifdef BOARD_NAII_68PPC2
4342
#define SYS_CLK (100000000) /* 100 MHz oscillator (NAII 68PPC2) */
43+
#else
44+
#define SYS_CLK (66666667) /* 66.66 MHz oscillator (T2080 RDB / CW VPX3-152) */
4445
#endif
4546

4647
/* ---- UART (PC16552D Dual UART) ---- */
@@ -214,34 +215,7 @@ enum ifc_amask_sizes {
214215

215216

216217
/* ---- DDR (T2080RM 12.4) ---- */
217-
#ifdef BOARD_VPX3152
218-
/* CW VPX3-152: DDR3L with ECC, 4/8/16 GB options, up to 1866 MT/s */
219-
/* TODO: Fill SPD parameters from DDR3L chip datasheet */
220-
#define DDR_N_RANKS 2 /* TODO: confirm from CS_CONFIG dump */
221-
#define DDR_RANK_DENS 0x100000000 /* TODO: confirm */
222-
#define DDR_SDRAM_WIDTH 64
223-
#define DDR_EC_SDRAM_W 8
224-
#define DDR_N_ROW_ADDR 16 /* TODO: confirm */
225-
#define DDR_N_COL_ADDR 10 /* TODO: confirm */
226-
#define DDR_N_BANKS 8
227-
#define DDR_EDC_CONFIG 2
228-
#define DDR_BURSTL_MASK 0x0c
229-
#define DDR_TCKMIN_X_PS 1500 /* TODO: from DDR3L datasheet */
230-
#define DDR_TCMMAX_PS 3000 /* TODO: from DDR3L datasheet */
231-
#define DDR_CASLAT_X 0x000007E0 /* TODO */
232-
#define DDR_TAA_PS 13500 /* TODO */
233-
#define DDR_TRCD_PS 13500 /* TODO */
234-
#define DDR_TRP_PS 13500 /* TODO */
235-
#define DDR_TRAS_PS 36000 /* TODO */
236-
#define DDR_TRC_PS 49500 /* TODO */
237-
#define DDR_TFAW_PS 30000 /* TODO */
238-
#define DDR_TWR_PS 15000 /* TODO */
239-
#define DDR_TRFC_PS 260000 /* TODO */
240-
#define DDR_TRRD_PS 6000 /* TODO */
241-
#define DDR_TWTR_PS 7500 /* TODO */
242-
#define DDR_TRTP_PS 7500 /* TODO */
243-
#define DDR_REF_RATE_PS 7800000 /* TODO */
244-
#else
218+
#ifdef BOARD_NAII_68PPC2
245219
/* NAII 68PPC2: 8GB discrete DDR3 IM8G08D3EBDG-15E */
246220
/* 1333.333 MT/s data rate 8 GiB (DDR3, 64-bit, CL=9, ECC on) */
247221
#define DDR_N_RANKS 2
@@ -268,10 +242,82 @@ enum ifc_amask_sizes {
268242
#define DDR_TWTR_PS 7500
269243
#define DDR_TRTP_PS 7500
270244
#define DDR_REF_RATE_PS 7800000
245+
#else
246+
/* T2080 RDB / CW VPX3-152: DDR3L SODIMM */
247+
/* TODO: Fill SPD parameters from DDR3L SODIMM datasheet */
248+
#define DDR_N_RANKS 2 /* TODO: confirm from CS_CONFIG dump */
249+
#define DDR_RANK_DENS 0x100000000 /* TODO: confirm */
250+
#define DDR_SDRAM_WIDTH 64
251+
#define DDR_EC_SDRAM_W 8
252+
#define DDR_N_ROW_ADDR 16 /* TODO: confirm */
253+
#define DDR_N_COL_ADDR 10 /* TODO: confirm */
254+
#define DDR_N_BANKS 8
255+
#define DDR_EDC_CONFIG 2
256+
#define DDR_BURSTL_MASK 0x0c
257+
#define DDR_TCKMIN_X_PS 1500 /* TODO: from DDR3L datasheet */
258+
#define DDR_TCMMAX_PS 3000 /* TODO: from DDR3L datasheet */
259+
#define DDR_CASLAT_X 0x000007E0 /* TODO */
260+
#define DDR_TAA_PS 13500 /* TODO */
261+
#define DDR_TRCD_PS 13500 /* TODO */
262+
#define DDR_TRP_PS 13500 /* TODO */
263+
#define DDR_TRAS_PS 36000 /* TODO */
264+
#define DDR_TRC_PS 49500 /* TODO */
265+
#define DDR_TFAW_PS 30000 /* TODO */
266+
#define DDR_TWR_PS 15000 /* TODO */
267+
#define DDR_TRFC_PS 260000 /* TODO */
268+
#define DDR_TRRD_PS 6000 /* TODO */
269+
#define DDR_TWTR_PS 7500 /* TODO */
270+
#define DDR_TRTP_PS 7500 /* TODO */
271+
#define DDR_REF_RATE_PS 7800000 /* TODO */
271272
#endif
272273

273-
#ifdef BOARD_VPX3152
274-
/* DDR register values from U-Boot on CW VPX3-152 board */
274+
#ifdef BOARD_NAII_68PPC2
275+
/* DDR register values from working U-Boot on NAII 68PPC2 board */
276+
#define DDR_CS0_BNDS_VAL 0x000000FF
277+
#define DDR_CS1_BNDS_VAL 0x010001FF
278+
#define DDR_CS2_BNDS_VAL 0x0300033F
279+
#define DDR_CS3_BNDS_VAL 0x0340037F
280+
#define DDR_CS0_CONFIG_VAL 0x80044402
281+
#define DDR_CS1_CONFIG_VAL 0x80044402
282+
#define DDR_CS2_CONFIG_VAL 0x00000202
283+
#define DDR_CS3_CONFIG_VAL 0x00040202
284+
#define DDR_CS_CONFIG_2_VAL 0x00000000
285+
286+
#define DDR_TIMING_CFG_0_VAL 0xFF530004
287+
#define DDR_TIMING_CFG_1_VAL 0x98906345
288+
#define DDR_TIMING_CFG_2_VAL 0x0040A114
289+
#define DDR_TIMING_CFG_3_VAL 0x010A1100
290+
#define DDR_TIMING_CFG_4_VAL 0x00000001
291+
#define DDR_TIMING_CFG_5_VAL 0x04402400
292+
293+
#define DDR_SDRAM_MODE_VAL 0x00441C70
294+
#define DDR_SDRAM_MODE_2_VAL 0x00980000
295+
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
296+
#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
297+
298+
#define DDR_SDRAM_CFG_VAL 0xE7040000
299+
#define DDR_SDRAM_CFG_2_VAL 0x00401000
300+
301+
#define DDR_SDRAM_INTERVAL_VAL 0x0C300100
302+
#define DDR_DATA_INIT_VAL 0xDEADBEEF
303+
#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000
304+
#define DDR_ZQ_CNTL_VAL 0x89080600
305+
306+
/* Write leveling - CRITICAL: board-specific values from U-Boot */
307+
#define DDR_WRLVL_CNTL_VAL 0x8675F604
308+
#define DDR_WRLVL_CNTL_2_VAL 0x05060607
309+
#define DDR_WRLVL_CNTL_3_VAL 0x080A0A0B
310+
311+
#define DDR_SDRAM_RCW_1_VAL 0x00000000
312+
#define DDR_SDRAM_RCW_2_VAL 0x00000000
313+
314+
#define DDR_DDRCDR_1_VAL 0x80040000
315+
#define DDR_DDRCDR_2_VAL 0x00000001
316+
317+
#define DDR_ERR_INT_EN_VAL 0x0000001D
318+
#define DDR_ERR_SBE_VAL 0x00010000
319+
#else
320+
/* T2080 RDB / CW VPX3-152: DDR register values */
275321
/* TODO: Fill ALL values from Phase 1 U-Boot register dump:
276322
* md.l 0xfe008000 4; md.l 0xfe008010 4 (CS BNDS)
277323
* md.l 0xfe008080 4; md.l 0xfe0080c0 4 (CS CONFIG)
@@ -321,51 +367,6 @@ enum ifc_amask_sizes {
321367
#define DDR_DDRCDR_1_VAL 0x00000000 /* TODO: from dump */
322368
#define DDR_DDRCDR_2_VAL 0x00000000 /* TODO: from dump */
323369

324-
#define DDR_ERR_INT_EN_VAL 0x0000001D
325-
#define DDR_ERR_SBE_VAL 0x00010000
326-
#else
327-
/* DDR values from working U-Boot on NAII 68PPC2 board */
328-
#define DDR_CS0_BNDS_VAL 0x000000FF
329-
#define DDR_CS1_BNDS_VAL 0x010001FF
330-
#define DDR_CS2_BNDS_VAL 0x0300033F
331-
#define DDR_CS3_BNDS_VAL 0x0340037F
332-
#define DDR_CS0_CONFIG_VAL 0x80044402
333-
#define DDR_CS1_CONFIG_VAL 0x80044402
334-
#define DDR_CS2_CONFIG_VAL 0x00000202
335-
#define DDR_CS3_CONFIG_VAL 0x00040202
336-
#define DDR_CS_CONFIG_2_VAL 0x00000000
337-
338-
#define DDR_TIMING_CFG_0_VAL 0xFF530004
339-
#define DDR_TIMING_CFG_1_VAL 0x98906345
340-
#define DDR_TIMING_CFG_2_VAL 0x0040A114
341-
#define DDR_TIMING_CFG_3_VAL 0x010A1100
342-
#define DDR_TIMING_CFG_4_VAL 0x00000001
343-
#define DDR_TIMING_CFG_5_VAL 0x04402400
344-
345-
#define DDR_SDRAM_MODE_VAL 0x00441C70
346-
#define DDR_SDRAM_MODE_2_VAL 0x00980000
347-
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
348-
#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
349-
350-
#define DDR_SDRAM_CFG_VAL 0xE7040000
351-
#define DDR_SDRAM_CFG_2_VAL 0x00401000
352-
353-
#define DDR_SDRAM_INTERVAL_VAL 0x0C300100
354-
#define DDR_DATA_INIT_VAL 0xDEADBEEF
355-
#define DDR_SDRAM_CLK_CNTL_VAL 0x02400000
356-
#define DDR_ZQ_CNTL_VAL 0x89080600
357-
358-
/* Write leveling - CRITICAL: board-specific values from U-Boot */
359-
#define DDR_WRLVL_CNTL_VAL 0x8675F604
360-
#define DDR_WRLVL_CNTL_2_VAL 0x05060607
361-
#define DDR_WRLVL_CNTL_3_VAL 0x080A0A0B
362-
363-
#define DDR_SDRAM_RCW_1_VAL 0x00000000
364-
#define DDR_SDRAM_RCW_2_VAL 0x00000000
365-
366-
#define DDR_DDRCDR_1_VAL 0x80040000
367-
#define DDR_DDRCDR_2_VAL 0x00000001
368-
369370
#define DDR_ERR_INT_EN_VAL 0x0000001D
370371
#define DDR_ERR_SBE_VAL 0x00010000
371372
#endif

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