Further code cleanups and optimizations

Author: dgarske

hal/nxp_p1021.c

@@ -34,31 +34,18 @@
 #define ENABLE_BUS_CLK_CALC
 
 #ifndef BUILD_LOADER_STAGE1
-    /* Tests */
-    #if 0
-        #define TEST_DDR
-        #define TEST_TPM
-    #endif
     #define ENABLE_PCIE
     #define ENABLE_CPLD /* Board Configuration and Status Registers (BCSR) */
     #define ENABLE_CONF_IO
     #define ENABLE_QE   /* QUICC Engine */
-    #if defined(WOLFBOOT_TPM) || defined(TEST_TPM)
+    #if defined(WOLFBOOT_TPM)
         #define ENABLE_ESPI /* SPI for TPM */
     #endif
     #define ENABLE_MP   /* multi-core support */
     #define ENABLE_IRQ
     /* #define ENABLE_QE_CRC32 */ /* CRC32 check on QE disabled by default */
 #endif
 
-/* Foward declarations */
-#if defined(ENABLE_DDR) && defined(TEST_DDR)
-static int test_ddr(void);
-#endif
-#if defined(ENABLE_ESPI) && defined(TEST_TPM)
-static int test_tpm(void);
-#endif
-
 #ifdef ENABLE_ESPI
 #include "spi_drv.h" /* for transfer flags and chip select */
 #endif
@@ -488,11 +475,7 @@ static uint32_t          flash_idx;
 int ext_flash_read(uintptr_t address, uint8_t *data, int len);
 #endif
 
-/* generic share NXP QorIQ driver code */
-#include "nxp_ppc.c"
-
-
-/* local functions */
+/* P1021 bus clock: reads GUTS_PORPLLSR (different from E5500/E6500 CLOCKING regs) */
 #ifdef ENABLE_BUS_CLK_CALC
 static uint32_t hal_get_bus_clk(void)
 {
@@ -508,53 +491,16 @@ static uint32_t hal_get_bus_clk(void)
 #define hal_get_bus_clk() (uint32_t)(SYS_CLK * 6)
 #endif
 
+/* E500 uses bus-clock based delay (not TIMEBASE like E5500/E6500) */
 #define DELAY_US (hal_get_bus_clk() / 1000000)
 static void udelay(uint32_t delay_us)
 {
     wait_ticks(delay_us * DELAY_US);
 }
 
-#if 0 /* useful timer code */
-
-uint64_t hal_timer_ms(void)
-{
-    uint64_t val;
-    /* time base is updated every 8 CCB clocks */
-    uint64_t cntfrq = hal_get_bus_clk() / 8;
-    uint64_t cntpct = get_ticks();
-    val = (cntpct * 1000ULL) / cntfrq;
-    return val;
-}
-
-/* example usage */
-//uint64_t start = hal_get_tick_count();
-// do some work
-//wolfBoot_printf("done (%lu ms)\n", (uint32_t)hal_elapsed_time_ms(start));
-
-/* Calculate elapsed time in milliseconds, handling timer overflow properly */
-uint64_t hal_elapsed_time_ms(uint64_t start_ticks)
-{
-    uint64_t current_ticks, elapsed_ticks;
-    uint64_t cntfrq = hal_get_bus_clk() / 8;
-
-    current_ticks = get_ticks();
-
-    /* Handle timer overflow using unsigned arithmetic
-     * This works correctly even if the timer has rolled over,
-     * as long as the elapsed time is less than the full timer range
-     */
-    elapsed_ticks = current_ticks - start_ticks;
-
-    /* Convert elapsed ticks to milliseconds */
-    return (elapsed_ticks * 1000ULL) / cntfrq;
-}
+/* generic share NXP QorIQ driver code (uart_init/uart_write use hal_get_bus_clk above) */
+#include "nxp_ppc.c"
 
-/* Get current tick count for use with hal_elapsed_time_ms() */
-uint64_t hal_get_tick_count(void)
-{
-    return get_ticks();
-}
-#endif
 
 /* ---- eSPI Driver ---- */
 #ifdef ENABLE_ESPI
@@ -673,47 +619,7 @@ void hal_espi_deinit(void)
 }
 #endif /* ENABLE_ESPI */
 
-/* ---- DUART Driver ---- */
-#ifdef DEBUG_UART
-
-void uart_init(void)
-{
-    /* calc divisor for UART
-     * baud rate = CCSRBAR frequency ÷ (16 x [UDMB||UDLB])
-     */
-    /* compute UART divisor - round up */
-    uint32_t div = (hal_get_bus_clk() + (16/2 * BAUD_RATE)) / (16 * BAUD_RATE);
-
-    while (!(get8(UART_LSR(UART_SEL)) & UART_LSR_TEMT))
-       ;
-
-    /* set ier, fcr, mcr */
-    set8(UART_IER(UART_SEL), 0);
-    set8(UART_FCR(UART_SEL), (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN));
-
-    /* enable baud rate access (DLAB=1) - divisor latch access bit*/
-    set8(UART_LCR(UART_SEL), (UART_LCR_DLAB | UART_LCR_WLS));
-    /* set divisor */
-    set8(UART_DLB(UART_SEL), (div & 0xff));
-    set8(UART_DMB(UART_SEL), ((div>>8) & 0xff));
-    /* disable rate access (DLAB=0) */
-    set8(UART_LCR(UART_SEL), (UART_LCR_WLS));
-}
-
-void uart_write(const char* buf, uint32_t sz)
-{
-    uint32_t pos = 0;
-    while (sz-- > 0) {
-        char c = buf[pos++];
-        if (c == '\n') { /* handle CRLF */
-            while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0);
-            set8(UART_THR(UART_SEL), '\r');
-        }
-        while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0);
-        set8(UART_THR(UART_SEL), c);
-    }
-}
-#endif /* DEBUG_UART */
+/* uart_init and uart_write are provided by nxp_ppc.c shared code */
 
 /* ---- eLBC Driver ---- */
 #ifdef ENABLE_ELBC

hal/nxp_ppc.c

@@ -21,3 +21,89 @@
 
 /* This file gets directly included from nxp_ targets.
  * This file contains shared driver code for all NXP QorIQ platforms */
+
+/* RAMFUNCTION is defined by image.h (included by targets that need RAM_CODE).
+ * Provide an empty fallback for targets that do not use RAM_CODE (e.g. T1024/P1021). */
+#ifndef RAMFUNCTION
+#define RAMFUNCTION
+#endif
+
+/* ---- E5500/E6500 clock helpers and udelay ----
+ * CLOCKING_PLLCNGSR and CLOCKING_PLLPGSR must be defined by the including
+ * target before this file is reached (e.g. via nxp_t2080.h / nxp_t1024.c).
+ * SYS_CLK must be the oscillator input frequency (e.g. 100 MHz). */
+#if defined(CORE_E5500) || defined(CORE_E6500)
+#ifdef ENABLE_BUS_CLK_CALC
+static uint32_t hal_get_core_clk(void)
+{
+    /* compute core clock: system_input * (CGA_PLL1_RAT / 2) */
+    uint32_t core_clk;
+    uint32_t core_ratio = get32(CLOCKING_PLLCNGSR(0));
+    core_ratio = ((core_ratio >> 1) & 0x3F);
+    core_clk = SYS_CLK * core_ratio;
+    return core_clk;
+}
+static uint32_t RAMFUNCTION hal_get_plat_clk(void)
+{
+    /* compute platform clock: system_input * (SYS_PLL_RAT / 2) */
+    uint32_t plat_clk;
+    uint32_t plat_ratio = get32(CLOCKING_PLLPGSR);
+    plat_ratio = ((plat_ratio >> 1) & 0x1F);
+    plat_clk = SYS_CLK * plat_ratio;
+    return plat_clk;
+}
+static uint32_t hal_get_bus_clk(void)
+{
+    return hal_get_plat_clk() / 2;
+}
+#endif /* ENABLE_BUS_CLK_CALC */
+
+#define TIMEBASE_CLK_DIV 16
+#define TIMEBASE_HZ (hal_get_plat_clk() / TIMEBASE_CLK_DIV)
+#define DELAY_US    (TIMEBASE_HZ / 1000000)
+static void RAMFUNCTION udelay(uint32_t delay_us)
+{
+    wait_ticks((unsigned long long)delay_us * DELAY_US);
+}
+#endif /* CORE_E5500 || CORE_E6500 */
+
+/* ---- Shared PC16552D-compatible DUART driver ----
+ * Each target must define before including this file:
+ *   UART_SEL, BAUD_RATE, UART_THR(n), UART_IER(n), UART_FCR(n),
+ *   UART_LCR(n), UART_DLB(n), UART_DMB(n), UART_LSR(n),
+ *   UART_FCR_TFR, UART_FCR_RFR, UART_FCR_FEN,
+ *   UART_LCR_DLAB, UART_LCR_WLS, UART_LSR_TEMT, UART_LSR_THRE */
+#ifdef DEBUG_UART
+void uart_init(void)
+{
+    /* baud rate = bus_clk / (16 * div); round up */
+    uint32_t div = (hal_get_bus_clk() + (8 * BAUD_RATE)) / (16 * BAUD_RATE);
+
+    while (!(get8(UART_LSR(UART_SEL)) & UART_LSR_TEMT))
+        ;
+
+    set8(UART_IER(UART_SEL), 0);
+    set8(UART_FCR(UART_SEL), (UART_FCR_TFR | UART_FCR_RFR | UART_FCR_FEN));
+
+    /* enable baud rate access (DLAB=1) */
+    set8(UART_LCR(UART_SEL), (UART_LCR_DLAB | UART_LCR_WLS));
+    set8(UART_DLB(UART_SEL), (div & 0xff));
+    set8(UART_DMB(UART_SEL), ((div >> 8) & 0xff));
+    /* disable baud rate access (DLAB=0) */
+    set8(UART_LCR(UART_SEL), (UART_LCR_WLS));
+}
+
+void uart_write(const char* buf, uint32_t sz)
+{
+    uint32_t pos = 0;
+    while (sz-- > 0) {
+        char c = buf[pos++];
+        if (c == '\n') { /* handle CRLF */
+            while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0);
+            set8(UART_THR(UART_SEL), '\r');
+        }
+        while ((get8(UART_LSR(UART_SEL)) & UART_LSR_THRE) == 0);
+        set8(UART_THR(UART_SEL), c);
+    }
+}
+#endif /* DEBUG_UART */

hal/nxp_ppc.h

@@ -111,10 +111,6 @@
     #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
 
-    /* relocate to 64-bit 0xE_ */
-    //#define CCSRBAR_PHYS_HIGH 0xEULL
-    //#define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
-
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
 
@@ -143,7 +139,11 @@
 
     #define ENABLE_DDR
     #ifndef DDR_SIZE
-    #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL)
+    #ifdef BOARD_VPX3152
+    #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* TODO: confirm from CS_BNDS dump (4/8/16 GB) */
+    #else
+    #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* NAII 68PPC2: 8 GB */
+    #endif
     #endif
 
     /* DDR stack configuration - relocate from CPC SRAM after DDR init
@@ -158,14 +158,25 @@
      * RAMFUNCTION code continues to work after CPC becomes L2 cache. */
     #define DDR_RAMCODE_ADDR  0x03000000UL       /* 48MB into DDR */
 
+    /* Flash base address and size — may differ between board variants.
+     * TODO: Confirm VPX3-152 flash mapping from IFC CSPR(0)/AMASK(0) dump.
+     * If the new board uses a different base address (e.g. 0xF0000000 for
+     * 256 MB flash), update the BOARD_VPX3152 values and uncomment. */
+#if 0 && defined(BOARD_VPX3152)
+    #define FLASH_BASE_ADDR      0xF0000000UL  /* TODO: from IFC dump */
+    #define FLASH_BASE_PHYS_HIGH 0x0ULL
+    #define FLASH_LAW_SIZE       LAW_SIZE_256MB
+    #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_256M
+#else
     #define FLASH_BASE_ADDR      0xE8000000UL
     #define FLASH_BASE_PHYS_HIGH 0x0ULL
     #define FLASH_LAW_SIZE       LAW_SIZE_128MB
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_128M
+#endif
 
     #define USE_LONG_JUMP
 #else
-    #error Please define platform PowerPC core version and CCSRBAR
+    #error Please define TARGET (nxp_t2080, nxp_t1024, or nxp_p1021)
 #endif
 
 
@@ -511,18 +522,16 @@ static inline void uart_putc_early(char c) { (void)c; }
     #define L2CSR1    0x3FA /* L2 Data Cache Control and Status Register 1 */
 #endif
 
-#define L2CSR0_L2FI  0x00200000 /* L2 Cache Flash Invalidate */
-#define L2CSR0_L2FL  0x00000800 /* L2 Cache Flush */
-#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
-#define L2CSR0_L2PE  0x40000000 /* L2 Cache Parity/ECC Enable */
 #define L2CSR0_L2E   0x80000000 /* L2 Cache Enable */
-
+#define L2CSR0_L2PE  0x40000000 /* L2 Cache Parity/ECC Enable */
 #define L2CSR0_L2WP  0x1c000000 /* L2 I/D Way Partioning */
 #define L2CSR0_L2CM  0x03000000 /* L2 Cache Coherency Mode */
 #define L2CSR0_L2FI  0x00200000 /* L2 Cache Flash Invalidate */
 #define L2CSR0_L2IO  0x00100000 /* L2 Cache Instruction Only */
 #define L2CSR0_L2DO  0x00010000 /* L2 Cache Data Only */
 #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
+#define L2CSR0_L2FL  0x00000800 /* L2 Cache Flush */
+#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
 
 
 #define SCCSRBAR  0x3FE /* Shifted CCSRBAR */
@@ -846,11 +855,6 @@ extern void dcache_disable(void);
 #define ENTRY_RESV        16
 #define ENTRY_PIR         20
 
-/* not used for ePAPR 1.1 */
-#define ENTRY_R6_UPPER    24
-#define ENTRY_R6_LOWER    28
-
-
 #define ENTRY_SIZE        64
 
 #endif /* !_NXP_PPC_H_ */