Progress with DDR (working now on NAII 6xppc2)

Author: dgarske

hal/nxp_ppc.h

@@ -118,17 +118,17 @@
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
 
-    /* T2080 CPC SRAM config - 512KB per T2080RM */
-    #define L2SRAM_ADDR   (0xF8F80000UL) /* CPC as SRAM (512KB) */
-    #define L2SRAM_SIZE   (512UL * 1024UL)
+    /* T2080 CPC SRAM config - 1MB for ECC P384 stack requirements */
+    #define L2SRAM_ADDR   (0xF8F00000UL) /* CPC as SRAM (1MB) */
+    #define L2SRAM_SIZE   (1024UL * 1024UL)
 
     #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
     /* CPC SRAM transactions traverse the CoreNet interconnect, which
      * requires a LAW to route them. LAW_TRGT_DDR_1 (0x10) is the CPC
      * target per T2080RM Table 2-2 (Target ID Assignments). */
-    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_512KB
+    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_1MB
     #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
-    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_512K
+    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M
 
     #define ENABLE_INTERRUPTS
 
@@ -593,6 +593,10 @@
 #endif
 
 #define mtspr(rn, v) __asm__ __volatile__("mtspr " WC_STRINGIFY(rn) ",%0" : : "r" (v))
+#define mfspr(rn) ({ \
+    unsigned int rval; \
+    __asm__ __volatile__("mfspr %0," WC_STRINGIFY(rn) : "=r" (rval)); rval; \
+})
 
 #define mfmsr() ({ \
     unsigned int rval; \

hal/nxp_t2080.c

@@ -230,7 +230,8 @@ void hal_ddr_init(void)
     set_law(4, 0, DDR_ADDRESS, LAW_TRGT_DDR_1, LAW_SIZE_2GB, 0);
 
     /* If DDR is already enabled then just return */
-    if (get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN) {
+    reg = get32(DDR_SDRAM_CFG);
+    if (reg & DDR_SDRAM_CFG_MEM_EN) {
         return;
     }
 
@@ -369,6 +370,129 @@ static void hal_cpld_init(void)
 #endif
 }
 
+#if defined(DEBUG_UART) && defined(ENABLE_DDR)
+/* DDR memory test - writes patterns and verifies readback */
+static int hal_ddr_test(void)
+{
+    volatile uint32_t *ddr = (volatile uint32_t *)DDR_ADDRESS;
+    uint32_t patterns[] = {0x55555555, 0xAAAAAAAA, 0x12345678, 0xDEADBEEF};
+    uint32_t test_offsets[] = {0, 0x100, 0x1000, 0x10000, 0x100000, 0x1000000};
+    int i, j;
+    int errors = 0;
+    uint32_t reg;
+
+    /* Show DDR controller status */
+    reg = get32(DDR_SDRAM_CFG);
+    wolfBoot_printf("DDR: SDRAM_CFG=0x%x (MEM_EN=%d)\n", reg,
+        (reg & DDR_SDRAM_CFG_MEM_EN) ? 1 : 0);
+    reg = get32(DDR_SDRAM_CFG_2);
+    wolfBoot_printf("DDR: SDRAM_CFG_2=0x%x (D_INIT=%d)\n", reg,
+        (reg & DDR_SDRAM_CFG_2_D_INIT) ? 1 : 0);
+
+    /* Show DDR LAW configuration (LAW 4) */
+    wolfBoot_printf("DDR LAW4: H=0x%x L=0x%x AR=0x%x\n",
+        get32(LAWBARH(4)), get32(LAWBARL(4)), get32(LAWAR(4)));
+
+    /* Read DDR TLB entry 12 using tlbre */
+    {
+        uint32_t mas0, mas1, mas2, mas3, mas7;
+        /* Select TLB1, entry 12 */
+        mas0 = (1 << 28) | (12 << 16); /* TLBSEL=1, ESEL=12 */
+        mtspr(MAS0, mas0);
+        __asm__ __volatile__("isync; tlbre; isync");
+        mas1 = mfspr(MAS1);
+        mas2 = mfspr(MAS2);
+        mas3 = mfspr(MAS3);
+        mas7 = mfspr(MAS7);
+        wolfBoot_printf("DDR TLB12: MAS1=0x%x MAS2=0x%x MAS3=0x%x MAS7=0x%x\n",
+            mas1, mas2, mas3, mas7);
+        /* Check if TLB entry is valid */
+        if (!(mas1 & 0x80000000)) {
+            wolfBoot_printf("DDR: ERROR - TLB12 not valid!\n");
+            return -1;
+        }
+    }
+
+    /* Check if DDR is enabled */
+    if (!(get32(DDR_SDRAM_CFG) & DDR_SDRAM_CFG_MEM_EN)) {
+        wolfBoot_printf("DDR: ERROR - Memory not enabled!\n");
+        return -1;
+    }
+
+    /* Check if DDR LAW is enabled */
+    reg = get32(LAWAR(4));
+    if (!(reg & LAWAR_ENABLE)) {
+        wolfBoot_printf("DDR: ERROR - LAW4 not enabled!\n");
+        return -1;
+    }
+
+    /* Show DDR chip select configuration */
+    wolfBoot_printf("DDR CS0: BNDS=0x%x CFG=0x%x\n",
+        get32(DDR_CS_BNDS(0)), get32(DDR_CS_CONFIG(0)));
+    wolfBoot_printf("DDR CS1: BNDS=0x%x CFG=0x%x\n",
+        get32(DDR_CS_BNDS(1)), get32(DDR_CS_CONFIG(1)));
+
+    /* Show DDR debug status registers */
+    wolfBoot_printf("DDR DDRDSR_1=0x%x DDRDSR_2=0x%x\n",
+        get32(DDR_DDRDSR_1), get32(DDR_DDRDSR_2));
+    wolfBoot_printf("DDR DDRCDR_1=0x%x DDRCDR_2=0x%x\n",
+        get32(DDR_DDRCDR_1), get32(DDR_DDRCDR_2));
+
+    /* Check for pre-existing DDR errors */
+    reg = get32(DDR_ERR_DETECT);
+    wolfBoot_printf("DDR ERR_DETECT=0x%x\n", reg);
+    if (reg != 0) {
+        wolfBoot_printf("DDR: ERROR - Pre-existing DDR errors!\n");
+        wolfBoot_printf("  Bit 31 (MME): %d - Multiple errors\n", (reg >> 31) & 1);
+        wolfBoot_printf("  Bit 7  (APE): %d - Address parity\n", (reg >> 7) & 1);
+        wolfBoot_printf("  Bit 3  (ACE): %d - Auto calibration\n", (reg >> 3) & 1);
+        wolfBoot_printf("  Bit 2  (CDE): %d - Correctable data\n", (reg >> 2) & 1);
+        wolfBoot_printf("DDR: Skipping memory test due to errors\n");
+        return -1;
+    }
+
+    wolfBoot_printf("DDR Test: base=0x%x\n", DDR_ADDRESS);
+    wolfBoot_printf("DDR: Attempting simple read at 0x%x...\n", DDR_ADDRESS);
+
+    /* First just try to read - don't write yet */
+    {
+        volatile uint32_t val = *ddr;
+        wolfBoot_printf("DDR: Read returned 0x%x\n", val);
+    }
+
+    for (i = 0; i < (int)(sizeof(test_offsets)/sizeof(test_offsets[0])); i++) {
+        uint32_t offset = test_offsets[i];
+        volatile uint32_t *addr = ddr + (offset / sizeof(uint32_t));
+
+        for (j = 0; j < (int)(sizeof(patterns)/sizeof(patterns[0])); j++) {
+            uint32_t pattern = patterns[j];
+            uint32_t readback;
+
+            /* Write pattern */
+            *addr = pattern;
+            __asm__ __volatile__("sync" ::: "memory");
+
+            /* Read back */
+            readback = *addr;
+
+            if (readback != pattern) {
+                wolfBoot_printf("  FAIL: @0x%x wrote 0x%x read 0x%x\n",
+                    (uint32_t)addr, pattern, readback);
+                errors++;
+            }
+        }
+    }
+
+    if (errors == 0) {
+        wolfBoot_printf("DDR Test: PASSED\n");
+    } else {
+        wolfBoot_printf("DDR Test: FAILED (%d errors)\n", errors);
+    }
+
+    return errors;
+}
+#endif /* DEBUG_UART && ENABLE_DDR */
+
 void hal_init(void)
 {
 #if defined(DEBUG_UART) && defined(ENABLE_CPLD)
@@ -401,6 +525,10 @@ void hal_init(void)
 #ifdef ENABLE_MP
     hal_mp_init();
 #endif
+
+#if defined(DEBUG_UART) && defined(ENABLE_DDR)
+    hal_ddr_test();
+#endif
 }
 
 static void hal_flash_unlock_sector(uint32_t sector)

hal/nxp_t2080.h

@@ -233,6 +233,7 @@ enum ifc_amask_sizes {
 #define DDR_TRTP_PS     7500
 #define DDR_REF_RATE_PS 7800000
 
+/* DDR values from working U-Boot on NAII 68PPC2 board */
 #define DDR_CS0_BNDS_VAL       0x000000FF
 #define DDR_CS1_BNDS_VAL       0x010001FF
 #define DDR_CS2_BNDS_VAL       0x0300033F
@@ -243,29 +244,30 @@ enum ifc_amask_sizes {
 #define DDR_CS3_CONFIG_VAL     0x00040202
 #define DDR_CS_CONFIG_2_VAL    0x00000000
 
-#define DDR_TIMING_CFG_0_VAL   0xFF550004
-#define DDR_TIMING_CFG_1_VAL   0xBCB48C56
-#define DDR_TIMING_CFG_2_VAL   0x0040C114
-#define DDR_TIMING_CFG_3_VAL   0x010C1000
+#define DDR_TIMING_CFG_0_VAL   0xFF530004
+#define DDR_TIMING_CFG_1_VAL   0x98906345
+#define DDR_TIMING_CFG_2_VAL   0x0040A114
+#define DDR_TIMING_CFG_3_VAL   0x010A1100
 #define DDR_TIMING_CFG_4_VAL   0x00000001
-#define DDR_TIMING_CFG_5_VAL   0x03402400
+#define DDR_TIMING_CFG_5_VAL   0x04402400
 
 #define DDR_SDRAM_MODE_VAL     0x00441C70
 #define DDR_SDRAM_MODE_2_VAL   0x00980000
 #define DDR_SDRAM_MODE_3_8_VAL 0x00000000
 #define DDR_SDRAM_MD_CNTL_VAL  0x00000000
 
-#define DDR_SDRAM_CFG_VAL      0xE7044000
-#define DDR_SDRAM_CFG_2_VAL    0x00401050
+#define DDR_SDRAM_CFG_VAL      0xE7040000
+#define DDR_SDRAM_CFG_2_VAL    0x00401000
 
 #define DDR_SDRAM_INTERVAL_VAL 0x0C300100
 #define DDR_DATA_INIT_VAL      0xDEADBEEF
 #define DDR_SDRAM_CLK_CNTL_VAL 0x02400000
 #define DDR_ZQ_CNTL_VAL        0x89080600
 
-#define DDR_WRLVL_CNTL_VAL     0x8675F608
-#define DDR_WRLVL_CNTL_2_VAL   0x080A0A0C
-#define DDR_WRLVL_CNTL_3_VAL   0x0C0E0E0D
+/* Write leveling - CRITICAL: board-specific values from U-Boot */
+#define DDR_WRLVL_CNTL_VAL     0x8675F604
+#define DDR_WRLVL_CNTL_2_VAL   0x05060607
+#define DDR_WRLVL_CNTL_3_VAL   0x080A0A0B
 
 #define DDR_SDRAM_RCW_1_VAL    0x00000000
 #define DDR_SDRAM_RCW_2_VAL    0x00000000
@@ -317,6 +319,7 @@ enum ifc_amask_sizes {
 #define DDR_DDRCDR_2       ((volatile uint32_t*)(DDR_BASE + 0xB2C)) /* DDR Control Driver Register 2 */
 #define DDR_DDRDSR_1       ((volatile uint32_t*)(DDR_BASE + 0xB20)) /* DDR Debug Status Register 1 */
 #define DDR_DDRDSR_2       ((volatile uint32_t*)(DDR_BASE + 0xB24)) /* DDR Debug Status Register 2 */
+#define DDR_ERR_DETECT     ((volatile uint32_t*)(DDR_BASE + 0xE40)) /* Memory error detect */
 #define DDR_ERR_DISABLE    ((volatile uint32_t*)(DDR_BASE + 0xE44)) /* Memory error disable */
 #define DDR_ERR_INT_EN     ((volatile uint32_t*)(DDR_BASE + 0xE48)) /* Memory error interrupt enable */
 #define DDR_ERR_SBE        ((volatile uint32_t*)(DDR_BASE + 0xE58)) /* Single-Bit ECC memory error management */

hal/nxp_t2080.ld

@@ -13,9 +13,9 @@ MEMORY
 {
     FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
 
-    /* CPC as SRAM - 512KB (T2080 supports up to 2MB, using 512KB)
+    /* CPC as SRAM - 1MB (T2080 supports up to 2MB, using 1MB for P384 stack)
      * Layout: .ramcode at bottom, stack grows down from top */
-    RAM (rwx) : ORIGIN = 0xF8F80000, LENGTH = 0x80000
+    RAM (rwx) : ORIGIN = 0xF8F00000, LENGTH = 0x100000
 
     /* DDR - 2GB */
     DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF

src/boot_ppc_start.S

@@ -596,8 +596,8 @@ cpc_poll_invalidate:
         stw     r0, CPCSRCR1(r1) /* SRAM high address = 0 */
         /* SRAM low address - use LOAD_ADDR32 on e6500 to avoid sign extension */
         LOAD_ADDR32(r0, L2SRAM_ADDR)
-        /* Enable SRAM and set size (must match L2SRAM_SIZE = 512KB) */
-        ori     r0, r0, (CPCSRCR0_SRAMSZ_512 | CPCSRCR0_SRAMEN)
+        /* Enable SRAM and set size (must match L2SRAM_SIZE = 1MB for P384) */
+        ori     r0, r0, (CPCSRCR0_SRAMSZ_1024 | CPCSRCR0_SRAMEN)
         stw     r0, CPCSRCR0(r1)
         mbar
         isync