More progress with startup issues

Author: dgarske

src/boot_ppc_start.S

@@ -917,24 +917,18 @@ cache_sram_init_loop:
         bdnz    cache_sram_init_loop
 #elif defined(L2SRAM_ADDR)
 cache_sram_init:
-        /* Zero CPC SRAM to initialize ECC/parity for all cache lines.
-         * Uses stdu (8-byte double-word stores with update) like the reference
-         * T2080 implementation.  dcbz cannot be used here because it generates
-         * a coherent "allocate-and-zero" CoreNet transaction that CPC SRAM
-         * does not support on cold power cycle.  stdu generates normal store
-         * transactions that work correctly through L1→L2→CPC SRAM.
-         * CPCPE (ECC) is disabled in SRAM mode, so line fills of uninitialized
-         * data do not trigger parity errors.  After zeroing, all SRAM is clean
-         * and safe for stack use. */
-        uart_putc_debug 'H'             /* checkpoint H: zeroing CPC SRAM */
-        LOAD_ADDR32(r2, L2SRAM_ADDR - 8)  /* stdu pre-decrements by 8 */
-        lis     r3, (L2SRAM_SIZE >> 3)@h   /* count = size / 8 (doublewords) */
-        ori     r3, r3, (L2SRAM_SIZE >> 3)@l
-        mtctr   r3
-        li      r3, 0
-1:      stdu    r3, 8(r2)
-        bdnz    1b
-        uart_putc_debug 'C'             /* checkpoint C: SRAM zeroed */
+        /* CPC SRAM: skip bulk zeroing.
+         * dcbz, stdu, and stw loops ALL hang on cold power cycle when doing
+         * bulk sequential writes to CPC SRAM.  The CPC SRAM is accessed via
+         * CoreNet fabric, and cache line fills/allocations through this path
+         * are unreliable before L1/L2 caches are fully operational.
+         * Individual stw stores (used by setup_stack stwu below) work fine.
+         * U-Boot avoids this entirely by using L1 dcache locking for initial
+         * stack and deferring CPC SRAM init to C code.
+         * TODO: Zero CPC SRAM from C code after DDR/cache init, or switch
+         * to L1 locked cache for initial stack (matching U-Boot approach). */
+        uart_putc_debug 'H'
+        uart_putc_debug 'C'
 #endif /* L1_CACHE_ADDR */
 
 setup_stack: