Progress with startup issues

Author: dgarske

hal/nxp_ppc.h

@@ -573,6 +573,7 @@ static inline void uart_putc_early(char c) { (void)c; }
 
 #define MSR_DS   (1<<4)  /* Book E Data address space */
 #define MSR_IS   (1<<5)  /* Book E Instruction address space */
+#define MSR_RI   (1<<1)  /* Recoverable Interrupt */
 #define MSR_DE   (1<<9)  /* Debug Exception Enable */
 #define MSR_ME   (1<<12) /* Machine check enable */
 #define MSR_EE   (1<<15) /* External Interrupt enable */

hal/nxp_t2080.c

@@ -669,6 +669,14 @@ void hal_init(void)
      * - Stack/data in DDR is cached by L1 D-cache + L2 + CPC */
     hal_reconfigure_cpc_as_cache();
     hal_flash_enable_caching();
+
+    /* Enable branch prediction now that DDR stack and cache hierarchy
+     * are fully configured.  Disabled during early ASM boot to avoid
+     * speculative fetches during hardware init. */
+    {
+        uint32_t bucsr = BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN;
+        __asm__ __volatile__("mtspr %0, %1; isync" :: "i"(SPRN_BUCSR), "r"(bucsr));
+    }
 #endif
 
 #ifdef ENABLE_MP

src/boot_ppc_start.S

@@ -244,9 +244,10 @@ hardware_reg:
 
 #ifndef BUILD_LOADER_STAGE1
 branch_prediction:
-        /* enable branch prediction */
-        lis     r0,     (BUCSR_ENABLE)@h
-        ori     r0, r0, (BUCSR_ENABLE)@l
+        /* Disable branch prediction during early boot.
+         * Enabled later in C after DDR stack relocation to avoid
+         * speculative fetches during hardware init. */
+        li      r0, 0
         mtspr   SPRN_BUCSR, r0
 #endif
 
@@ -559,15 +560,14 @@ flash_law:
         lwz     r2, 8(r9)
         isync
 flash_tlb:
-        /* Flash: TLB 1, Entry 2, Super X/R/W, W/I/G, TS=0, 64/128M, IPROT */
-        /* Write is required for Write/Erase using CFI commands to base */
-    #ifdef BUILD_LOADER_STAGE1
-        /* Using XIP from this flash, so cannot use cache inhibit */
+        /* Flash: TLB 1, Entry 2, Super X/R/W, W+G, TS=0, 64/128M, IPROT
+         * Write-through (W) enables L1 I-cache to cache flash instruction
+         * fetches during XIP boot — matches reference T2080 implementation.
+         * Guarded (G) prevents speculative prefetches to the IFC.
+         * After DDR stack relocation, C code switches to I|G for flash
+         * write/erase (hal_flash_cache_disable) or M for full caching
+         * (hal_flash_enable_caching). */
         #define FLASH_TLB_WING (MAS2_W | MAS2_G)
-    #else
-        /* IFC polling requires cache inhibit */
-        #define FLASH_TLB_WING (MAS2_I | MAS2_G)
-    #endif
         set_tlb(1, 2,
                 FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
                 MAS3_SX | MAS3_SW | MAS3_SR, FLASH_TLB_WING, 0,
@@ -917,15 +917,24 @@ cache_sram_init_loop:
         bdnz    cache_sram_init_loop
 #elif defined(L2SRAM_ADDR)
 cache_sram_init:
-        /* CPC SRAM: no dcbz init needed.
-         * dcbz generates a coherent "allocate-and-zero" transaction on CoreNet.
-         * On cold power cycle this transaction hangs (CPC SRAM does not support
-         * it before the first regular store hits the SRAM).  Since CPCPE (ECC)
-         * is intentionally disabled in SRAM mode, there are no parity bits to
-         * initialize.  The stack stores in setup_stack below use regular stw,
-         * which CPC SRAM handles correctly. */
-        uart_putc_debug 'H'             /* checkpoint H: skipping dcbz, entering setup_stack */
-        uart_putc_debug 'C'             /* checkpoint C: (skipped dcbz loop) */
+        /* Zero CPC SRAM to initialize ECC/parity for all cache lines.
+         * Uses stdu (8-byte double-word stores with update) like the reference
+         * T2080 implementation.  dcbz cannot be used here because it generates
+         * a coherent "allocate-and-zero" CoreNet transaction that CPC SRAM
+         * does not support on cold power cycle.  stdu generates normal store
+         * transactions that work correctly through L1→L2→CPC SRAM.
+         * CPCPE (ECC) is disabled in SRAM mode, so line fills of uninitialized
+         * data do not trigger parity errors.  After zeroing, all SRAM is clean
+         * and safe for stack use. */
+        uart_putc_debug 'H'             /* checkpoint H: zeroing CPC SRAM */
+        LOAD_ADDR32(r2, L2SRAM_ADDR - 8)  /* stdu pre-decrements by 8 */
+        lis     r3, (L2SRAM_SIZE >> 3)@h   /* count = size / 8 (doublewords) */
+        ori     r3, r3, (L2SRAM_SIZE >> 3)@l
+        mtctr   r3
+        li      r3, 0
+1:      stdu    r3, 8(r2)
+        bdnz    1b
+        uart_putc_debug 'C'             /* checkpoint C: SRAM zeroed */
 #endif /* L1_CACHE_ADDR */
 
 setup_stack:
@@ -945,9 +954,9 @@ setup_stack:
         stwu    r1, -8(r1)   /* Save back chain and move SP */
         stw     r0, +12(r1)  /* Save return addr (underflow vect) */
 
-        /* switch back to AS/TS=0 */
-        lis     r3,     (MSR_CE | MSR_ME | MSR_DE)@h
-        ori     r3, r3, (MSR_CE | MSR_ME | MSR_DE)@l
+        /* switch back to AS/TS=0, enable recoverable interrupts */
+        lis     r3,     (MSR_CE | MSR_ME | MSR_DE | MSR_RI)@h
+        ori     r3, r3, (MSR_CE | MSR_ME | MSR_DE | MSR_RI)@l
         mtmsr   r3
         isync
         uart_putc_debug 'D'             /* checkpoint D: stack ready, entering C */