Peer review fixes

Author: dgarske

config/examples/nxp-t2080.config

@@ -38,8 +38,8 @@ OPTIMIZATION_LEVEL?=1
 # NOR Base Address
 ARCH_FLASH_OFFSET?=0xEFFE0000
 
-# Flash Sector Size
-WOLFBOOT_SECTOR_SIZE?=0x10000
+# Flash Sector Size (must match physical NOR erase block: 128 KB)
+WOLFBOOT_SECTOR_SIZE?=0x20000
 
 # wolfBoot start address
 WOLFBOOT_ORIGIN?=0xEFFE0000

docs/Targets.md

@@ -3266,7 +3266,7 @@ Build: Feb 27 2026 12:27:15
 IFC CSPR0: 0x141 (WP set)
 DDR Test: PASSED
 Ramcode: copied 5584 bytes to DDR, TLB9 remapped
-CPC: Released SRAM, full 2MB L2 cache enabled
+CPC: Released SRAM, full 2MB L3 CPC cache enabled
 Flash: caching enabled (L1+L2+CPC)
 MP: Starting cores (boot page 0x7FFFF000, spin table 0x7FFFE100)
 Internal flash test at 0xEFFA0000

hal/nxp_t2080.c

@@ -590,11 +590,13 @@ static int RAMFUNCTION hal_flash_status_wait(uint32_t sector, uint32_t timeout_u
     uint32_t timeout = 0;
     uint16_t read1, read2;
 
-    /* Replicate 8-bit AMD toggle bit to both bytes for parallel chips */
+    /* Replicate 8-bit AMD toggle/error bits to both bytes for parallel chips */
 #if FLASH_CFI_WIDTH == 16
     uint16_t toggle16 = (AMD_STATUS_TOGGLE << 8) | AMD_STATUS_TOGGLE;
+    uint16_t error16  = (AMD_STATUS_ERROR  << 8) | AMD_STATUS_ERROR;
 #else
     uint16_t toggle16 = AMD_STATUS_TOGGLE;
+    uint16_t error16  = AMD_STATUS_ERROR;
 #endif
 
     do {
@@ -618,7 +620,7 @@ static int RAMFUNCTION hal_flash_status_wait(uint32_t sector, uint32_t timeout_u
         if (((read1 ^ read2) & toggle16) == 0)
             break;
         /* Check DQ5 (error) on both chips while still toggling */
-        if (read1 & ((AMD_STATUS_ERROR << 8) | AMD_STATUS_ERROR)) {
+        if (read1 & error16) {
             /* Read one more time to confirm it's not a false DQ5 */
 #if FLASH_CFI_WIDTH == 16
             read1 = FLASH_IO16_READ(sector, 0);
@@ -811,6 +813,10 @@ extern uint32_t _secondary_start_page;
 extern uint32_t _second_half_boot_page;
 extern uint32_t _spin_table[];
 extern uint32_t _spin_table_addr;
+
+/* DDR address of the spin table, set during hal_mp_init() and reused in
+ * hal_dts_fixup() for cpu-release-addr fixups. */
+static uint32_t g_spin_table_ddr = 0;
 extern uint32_t _bootpg_addr;
 
 /* Startup additional cores with spin table and synchronize the timebase.
@@ -950,6 +956,9 @@ static void hal_mp_init(void)
     }
     flush_cache(second_half_ddr, BOOT_ROM_SIZE);
 
+    /* Persist DDR spin-table base for use in hal_dts_fixup() */
+    g_spin_table_ddr = spin_table_ddr;
+
     /* start cores and wait for them to be enabled */
     hal_mp_up(bootpg, spin_table_ddr);
 }
@@ -1021,9 +1030,11 @@ int hal_dts_fixup(void* dts_addr)
         }
 
     #ifdef ENABLE_MP
-        /* calculate location of spin table for core */
-        core_spin_table = (uint64_t)((uintptr_t)(
-                  (uint8_t*)_spin_table + (core * ENTRY_SIZE)));
+        /* Calculate DDR address of this core's spin table entry.
+         * Must use g_spin_table_ddr (the DDR copy), NOT _spin_table which
+         * is the flash/VMA address — Linux writes the release word to this
+         * address, and XIP flash is read-only. */
+        core_spin_table = (uint64_t)(g_spin_table_ddr + (core * ENTRY_SIZE));
 
         fdt_fixup_str(fdt, off, "cpu", "status", (core == 0) ? "okay" : "disabled");
         fdt_fixup_val64(fdt, off, "cpu", "cpu-release-addr", core_spin_table);