Vorago VA416xx port improvements

Author: dgarske

docs/Targets.md

@@ -4705,7 +4705,7 @@ The default build uses DEBUG_UART=1 to generate logging on the UART.
 
 ```sh
 cp config/examples/vorago_va416x0.config .config
-make VORAGO_SDK_DIR=$PWD../VA416xx_SDK/
+make VORAGO_SDK_DIR=$PWD/../VA416xx_SDK/
         [CC ARM] src/string.o
         [CC ARM] src/image.o
         [CC ARM] src/libwolfboot.o
@@ -4850,6 +4850,7 @@ echo -n "pBOOT" > trigger_magic.bin
         0x3F7FB trigger_magic.bin
 
 # Use JLink to load
+#JLinkExe -CommanderScript tools/scripts/va416x0/flash_va416xx_update.jlink
 device VA416XX
 si 1
 speed 2000

hal/va416x0.c

@@ -237,6 +237,15 @@ hal_status_t FRAM_Write(uint8_t spiBank, uint32_t addr, uint8_t *buf,
     hal_status_t status = hal_status_ok;
     uint8_t spiData[4];
 
+    /* Validate input parameters */
+    if (buf == NULL || len == 0) {
+        return hal_status_badParam;
+    }
+    /* Bounds check: ensure write doesn't exceed FRAM size */
+    if (addr >= FRAM_SIZE || (addr + len) > FRAM_SIZE) {
+        return hal_status_badParam;
+    }
+
 #ifdef DEBUG_EXT_FLASH
     wolfBoot_printf("fram write: addr 0x%x, dst 0x%x, len %d\n",
         addr, buf, len);
@@ -259,6 +268,15 @@ hal_status_t FRAM_Read(uint8_t spiBank, uint32_t addr, uint8_t *buf,
 {
     uint8_t spiData[4];
 
+    /* Validate input parameters */
+    if (buf == NULL || len == 0) {
+        return hal_status_badParam;
+    }
+    /* Bounds check: ensure read doesn't exceed FRAM size */
+    if (addr >= FRAM_SIZE || (addr + len) > FRAM_SIZE) {
+        return hal_status_badParam;
+    }
+
 #ifdef DEBUG_EXT_FLASH
     wolfBoot_printf("fram read: addr 0x%x, dst 0x%x, len %d\n",
         addr, buf, len);
@@ -290,7 +308,7 @@ hal_status_t FRAM_Erase(uint8_t spiBank, uint32_t addr, uint32_t len)
     memset(data, FRAM_ERASE_VALUE, sizeof(data));
 
     while (len > 0) {
-        int erase_len = (len > (int)sizeof(data)) ? (int)sizeof(data) : len;
+        uint32_t erase_len = (len > sizeof(data)) ? sizeof(data) : len;
         status = FRAM_Write(ROM_SPI_BANK, addr, data, erase_len);
         if (status != hal_status_ok) {
             return -(int)status; /* convert to negative error code */
@@ -333,14 +351,14 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 #ifdef EXT_FLASH
 void ext_flash_lock(void)
 {
-    /* Enable writes to code memory space */
-    VOR_SYSCONFIG->ROM_PROT |= SYSCONFIG_ROM_PROT_WREN_Msk;
+    /* Disable writes to code memory space */
+    VOR_SYSCONFIG->ROM_PROT &= ~SYSCONFIG_ROM_PROT_WREN_Msk;
 }
 
 void ext_flash_unlock(void)
 {
-    /* Disable writes to code memory space */
-    VOR_SYSCONFIG->ROM_PROT &= ~SYSCONFIG_ROM_PROT_WREN_Msk;
+    /* Enable writes to code memory space */
+    VOR_SYSCONFIG->ROM_PROT |= SYSCONFIG_ROM_PROT_WREN_Msk;
 }
 
 int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
@@ -480,12 +498,12 @@ void hal_init(void)
     }
 
     /* Disable Watchdog - should be already disabled out of reset */
-    VOR_WATCH_DOG->WDOGLOCK    = 0x1ACCE551;
+    VOR_WATCH_DOG->WDOGLOCK    = WATCHDOG_UNLOCK_KEY;
     VOR_WATCH_DOG->WDOGCONTROL = 0x0;
     NVIC_ClearPendingIRQ(WATCHDOG_IRQn);
 
     /* set FPU CP10 and CP11 Full Access */
-    SCB->CPACR |= ((0x3 << 20)|(0x3 << 22));
+    SCB->CPACR |= (CPACR_CP10_FULL_ACCESS | CPACR_CP11_FULL_ACCESS);
 
     /* Init EDAC */
     ConfigEdac(WOLFBOOT_EDAC_RAM_SCRUB, WOLFBOOT_EDAC_ROM_SCRUB);

hal/va416x0.h

@@ -20,8 +20,8 @@
  */
 
 
-#ifndef VA416X0_DEF_INCLUDED
-#define VA416X0_DEF_INCLUDED
+#ifndef WOLFBOOT_HAL_VA416X0_H
+#define WOLFBOOT_HAL_VA416X0_H
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -108,4 +108,12 @@
 #endif
 
 
-#endif /* VA416X0_DEF_INCLUDED */
+/* Watchdog unlock key - required to modify watchdog registers */
+#define WATCHDOG_UNLOCK_KEY         0x1ACCE551
+
+/* FPU Coprocessor Access Control - enable CP10 and CP11 full access */
+#define CPACR_CP10_FULL_ACCESS      (0x3 << 20)
+#define CPACR_CP11_FULL_ACCESS      (0x3 << 22)
+
+
+#endif /* WOLFBOOT_HAL_VA416X0_H */