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dgarskedanielinux
dgarske
authored and
danielinux
committed
Fix the NXP T2080 settings for the Curtiss-Wright VPX3-152 board (BOARD_CW_VPX3152).
1 parent 968e5bf commit 96828c1

3 files changed

Lines changed: 102 additions & 15 deletions

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‎config/examples/nxp-t2080.config‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,32 +36,41 @@ WOLFTPM?=0
3636
OPTIMIZATION_LEVEL?=1
3737

3838
# NOR Base Address
39+
# T2080 RDB: 128MB flash at 0xE8000000, wolfBoot at top (0xEFFE0000)
40+
# CW VPX3-152: 256MB flash at 0xF0000000, wolfBoot at top (0xFFFE0000)
3941
ARCH_FLASH_OFFSET?=0xEFFE0000
42+
#ARCH_FLASH_OFFSET?=0xFFFE0000 # CW VPX3-152
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4144
# Flash Sector Size
4245
WOLFBOOT_SECTOR_SIZE?=0x10000
4346

4447
# wolfBoot start address
4548
WOLFBOOT_ORIGIN?=0xEFFE0000
49+
#WOLFBOOT_ORIGIN?=0xFFFE0000 # CW VPX3-152
4650
# wolfBoot partition size (custom)
4751
BOOTLOADER_PARTITION_SIZE=0x20000
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4953
# Application Partition Size
5054
WOLFBOOT_PARTITION_SIZE?=0x100000
5155
# Location in Flash for Application Partition
5256
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFEE0000
57+
#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xFFEE0000 # CW VPX3-152
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# Load Partition to RAM Address
5459
WOLFBOOT_LOAD_ADDRESS?=0x19000
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5661
# Location in Flash for Update Partition
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFDE0000
63+
#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xFFDE0000 # CW VPX3-152
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# Location of temporary sector used during updates
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFDD0000
67+
#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFDD0000 # CW VPX3-152
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6269
# DTS (Device Tree)
6370
WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
71+
#WOLFBOOT_DTS_BOOT_ADDRESS?=0xF0040000 # CW VPX3-152
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WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
73+
#WOLFBOOT_DTS_UPDATE_ADDRESS?=0xF0050000 # CW VPX3-152
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# DTS Load to RAM Address
6675
WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
6776

‎hal/nxp_ppc.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@
140140
#define ENABLE_DDR
141141
#ifndef DDR_SIZE
142142
#ifdef BOARD_CW_VPX3152
143-
#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* TODO: confirm from CS_BNDS dump (4/8/16 GB) */
143+
#define DDR_SIZE (4096ULL * 1024ULL * 1024ULL) /* CW VPX3-152: 4 GB (CS0_BNDS=0x000000FF, CS1 disabled) */
144144
#else
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#define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* T2080 RDB / NAII 68PPC2: 8 GB */
146146
#endif
@@ -158,13 +158,13 @@
158158
* RAMFUNCTION code continues to work after CPC becomes L2 cache. */
159159
#define DDR_RAMCODE_ADDR 0x03000000UL /* 48MB into DDR */
160160

161-
/* Flash base address and size — may differ between board variants.
162-
* TODO: Confirm VPX3-152 flash mapping from IFC CSPR(0)/AMASK(0) dump.
163-
* If the new board uses a different base address (e.g. 0xF0000000 for
164-
* 256 MB flash), update the BOARD_CW_VPX3152 values and uncomment. */
165-
#if 0 && defined(BOARD_CW_VPX3152)
166-
#define FLASH_BASE_ADDR 0xF0000000UL /* TODO: from IFC dump */
167-
#define FLASH_BASE_PHYS_HIGH 0x0ULL
161+
/* Flash base address and size.
162+
* CW VPX3-152: 256 MB NOR at 0xF_F000_0000
163+
* Confirmed from U-Boot: IFC CSPR(0)=0xF0000105 (EXT=0xF), AMASK(0)=0xF0000000,
164+
* LAW0: addr=0xF_F000_0000, size=256MB, target=IFC. */
165+
#ifdef BOARD_CW_VPX3152
166+
#define FLASH_BASE_ADDR 0xF0000000UL /* 256MB NOR flash (0xF0000000-0xFFFFFFFF) */
167+
#define FLASH_BASE_PHYS_HIGH 0xFULL
168168
#define FLASH_LAW_SIZE LAW_SIZE_256MB
169169
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_256M
170170
#else

‎hal/nxp_t2080.h‎

Lines changed: 85 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,13 @@
1919
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
2020
*
2121
* Board support:
22-
* Default: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
23-
* BOARD_CW_VPX3152: CW VPX3-152 (66.667 MHz oscillator, DDR3L)
22+
* Default: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
23+
* BOARD_CW_VPX3152: Curtiss-Wright VPX3-152 (66.667 MHz oscillator,
24+
* 4GB DDR3L single-rank, 256MB NOR flash at 0xF0000000)
2425
* BOARD_NAII_68PPC2: NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
2526
*
26-
* NXP T2080E Rev 1.1, e6500 core 2.0, PVR 8040_0120 and SVR 8538_0011
27+
* NXP T2080E Rev 1.1, e6500 core 2.0, PVR=0x80400120 SVR=0x85380011
28+
* (confirmed on CW VPX3-152 via U-Boot: md.l 0xfe0e00a0 2)
2729
*/
2830

2931
#ifndef NXP_T2080_H
@@ -141,7 +143,11 @@ enum ifc_amask_sizes {
141143

142144

143145
/* ---- NOR Flash ---- */
144-
#define FLASH_BANK_SIZE (128*1024*1024)
146+
#ifdef BOARD_CW_VPX3152
147+
#define FLASH_BANK_SIZE (256*1024*1024) /* 256MB NOR flash (IFC CS0 AMASK=0xF0000000) */
148+
#else
149+
#define FLASH_BANK_SIZE (128*1024*1024) /* 128MB NOR flash */
150+
#endif
145151
#define FLASH_PAGE_SIZE (512) /* program buffer (256 bytes per chip x 2 chips) */
146152
#define FLASH_SECTOR_SIZE (128*1024)
147153
#define FLASH_SECTORS (FLASH_BANK_SIZE / FLASH_SECTOR_SIZE)
@@ -242,8 +248,35 @@ enum ifc_amask_sizes {
242248
#define DDR_TWTR_PS 7500
243249
#define DDR_TRTP_PS 7500
244250
#define DDR_REF_RATE_PS 7800000
251+
#elif defined(BOARD_CW_VPX3152)
252+
/* CW VPX3-152: 4 GB single-rank DDR3L
253+
* Confirmed from U-Boot: CS0_BNDS=0x000000FF (4GB), CS1_CONFIG bit31=0 (disabled) */
254+
#define DDR_N_RANKS 1 /* CS0 only; CS1 disabled (CS1_CONFIG=0x00014402) */
255+
#define DDR_RANK_DENS 0x100000000 /* 4 GB per rank */
256+
#define DDR_SDRAM_WIDTH 64
257+
#define DDR_EC_SDRAM_W 8
258+
#define DDR_N_ROW_ADDR 16
259+
#define DDR_N_COL_ADDR 10
260+
#define DDR_N_BANKS 8
261+
#define DDR_EDC_CONFIG 2
262+
#define DDR_BURSTL_MASK 0x0c
263+
#define DDR_TCKMIN_X_PS 1500 /* DDR3-1333 (from TIMING_CFG_3=0x020E1100) */
264+
#define DDR_TCMMAX_PS 3000
265+
#define DDR_CASLAT_X 0x000007E0
266+
#define DDR_TAA_PS 13500
267+
#define DDR_TRCD_PS 13500
268+
#define DDR_TRP_PS 13500
269+
#define DDR_TRAS_PS 36000
270+
#define DDR_TRC_PS 49500
271+
#define DDR_TFAW_PS 30000
272+
#define DDR_TWR_PS 15000
273+
#define DDR_TRFC_PS 260000
274+
#define DDR_TRRD_PS 6000
275+
#define DDR_TWTR_PS 7500
276+
#define DDR_TRTP_PS 7500
277+
#define DDR_REF_RATE_PS 7800000
245278
#else
246-
/* T2080 RDB / CW VPX3-152: DDR3L SODIMM */
279+
/* T2080 RDB: DDR3L SODIMM */
247280
/* TODO: Fill SPD parameters from DDR3L SODIMM datasheet */
248281
#define DDR_N_RANKS 2 /* TODO: confirm from CS_CONFIG dump */
249282
#define DDR_RANK_DENS 0x100000000 /* TODO: confirm */
@@ -314,10 +347,55 @@ enum ifc_amask_sizes {
314347
#define DDR_DDRCDR_1_VAL 0x80040000
315348
#define DDR_DDRCDR_2_VAL 0x00000001
316349

350+
#define DDR_ERR_INT_EN_VAL 0x0000001D
351+
#define DDR_ERR_SBE_VAL 0x00010000
352+
#elif defined(BOARD_CW_VPX3152)
353+
/* CW VPX3-152: DDR register values from U-Boot hardware dump */
354+
#define DDR_CS0_BNDS_VAL 0x000000FF /* CS0: 0-4GB (4GB rank) */
355+
#define DDR_CS1_BNDS_VAL 0x00000000 /* CS1: disabled */
356+
#define DDR_CS2_BNDS_VAL 0x00000000
357+
#define DDR_CS3_BNDS_VAL 0x00000000
358+
#define DDR_CS0_CONFIG_VAL 0x80014402 /* CS0 enabled */
359+
#define DDR_CS1_CONFIG_VAL 0x00014402 /* CS1 disabled (bit31=0) */
360+
#define DDR_CS2_CONFIG_VAL 0x00000000
361+
#define DDR_CS3_CONFIG_VAL 0x00000000
362+
#define DDR_CS_CONFIG_2_VAL 0x00000000
363+
364+
#define DDR_TIMING_CFG_3_VAL 0x020E1100
365+
#define DDR_TIMING_CFG_0_VAL 0x8066000F
366+
#define DDR_TIMING_CFG_1_VAL 0xD0D8B067
367+
#define DDR_TIMING_CFG_2_VAL 0x0049315A
368+
#define DDR_TIMING_CFG_4_VAL 0x00000001
369+
#define DDR_TIMING_CFG_5_VAL 0x05401400
370+
371+
#define DDR_SDRAM_MODE_VAL 0x00461014
372+
#define DDR_SDRAM_MODE_2_VAL 0x00A00000
373+
#define DDR_SDRAM_MODE_3_8_VAL 0x00000000
374+
#define DDR_SDRAM_MD_CNTL_VAL 0x00000000
375+
376+
#define DDR_SDRAM_CFG_VAL 0xE7240000 /* MEM_EN|SREN|ECC_EN, DDR3 */
377+
#define DDR_SDRAM_CFG_2_VAL 0x00401000 /* ODT_CFG, NUM_PR=1 */
378+
379+
#define DDR_SDRAM_INTERVAL_VAL 0x0E3C071C
380+
#define DDR_DATA_INIT_VAL 0xDEADBEEF /* ECC init pattern */
381+
#define DDR_SDRAM_CLK_CNTL_VAL 0x01400000
382+
#define DDR_ZQ_CNTL_VAL 0x8A090700
383+
384+
/* Write leveling - board-specific PCB trace delays */
385+
#define DDR_WRLVL_CNTL_VAL 0x8655F604
386+
#define DDR_WRLVL_CNTL_2_VAL 0x05030709
387+
#define DDR_WRLVL_CNTL_3_VAL 0x0E090D08
388+
389+
#define DDR_SDRAM_RCW_1_VAL 0x00000000 /* unbuffered DDR3L */
390+
#define DDR_SDRAM_RCW_2_VAL 0x00000000
391+
392+
#define DDR_DDRCDR_1_VAL 0x80000000
393+
#define DDR_DDRCDR_2_VAL 0x00000001
394+
317395
#define DDR_ERR_INT_EN_VAL 0x0000001D
318396
#define DDR_ERR_SBE_VAL 0x00010000
319397
#else
320-
/* T2080 RDB / CW VPX3-152: DDR register values */
398+
/* T2080 RDB: DDR register values */
321399
/* TODO: Fill ALL values from Phase 1 U-Boot register dump:
322400
* md.l 0xfe008000 4; md.l 0xfe008010 4 (CS BNDS)
323401
* md.l 0xfe008080 4; md.l 0xfe0080c0 4 (CS CONFIG)
@@ -335,10 +413,10 @@ enum ifc_amask_sizes {
335413
#define DDR_CS3_CONFIG_VAL 0x00000000 /* TODO: from dump */
336414
#define DDR_CS_CONFIG_2_VAL 0x00000000 /* TODO: from dump */
337415

416+
#define DDR_TIMING_CFG_3_VAL 0x00000000 /* TODO: from dump */
338417
#define DDR_TIMING_CFG_0_VAL 0x00000000 /* TODO: from dump */
339418
#define DDR_TIMING_CFG_1_VAL 0x00000000 /* TODO: from dump */
340419
#define DDR_TIMING_CFG_2_VAL 0x00000000 /* TODO: from dump */
341-
#define DDR_TIMING_CFG_3_VAL 0x00000000 /* TODO: from dump */
342420
#define DDR_TIMING_CFG_4_VAL 0x00000000 /* TODO: from dump */
343421
#define DDR_TIMING_CFG_5_VAL 0x00000000 /* TODO: from dump */
344422

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