Relocation to DDR and enabling cache

Author: dgarske

docs/Targets.md

@@ -3129,12 +3129,22 @@ Example Boot Debug Output:
 
 ```
 wolfBoot Init
-Part: Active 0, Address E8080000
-Image size 1028
+Build: Feb 19 2026 13:24:56
+DDR Test: PASSED
+Ramcode: copied 2852 bytes to DDR, TLB9 remapped
+CPC: Released SRAM, full 2MB L2 cache enabled
+Flash: caching enabled (L1+L2+CPC)
+Versions: Boot 1, Update 0
+Trying Boot partition at 0xEFFC0000
+Boot partition: 0xEFFC0000 (sz 3164, ver 0x1, type 0x601)
+Checking integrity...done
+Verifying signature...done
+Successfully selected image in part: 0
 Firmware Valid
-Loading 1028 bytes to RAM at 19000
-Failed parsing DTB to load.
-Booting at 19000
+Copying image from 0xEFFC0200 to RAM at 0x19000 (3164 bytes)
+Failed parsing DTB to load
+Booting at 0x19000
+FDT: Invalid header! -1
 Test App
 
 0x00000001

hal/nxp_ppc.h

@@ -144,6 +144,11 @@
     #define DDR_STACK_TOP     0x02000000UL       /* Top of first 32MB */
     #define DDR_STACK_BASE    (DDR_STACK_TOP - DDR_STACK_SIZE)
 
+    /* DDR address where .ramcode is copied before CPC SRAM is released.
+     * TLB9 is remapped: VA 0xF8F00000 -> PA DDR_RAMCODE_ADDR so that
+     * RAMFUNCTION code continues to work after CPC becomes L2 cache. */
+    #define DDR_RAMCODE_ADDR  0x03000000UL       /* 48MB into DDR */
+
     #define FLASH_BASE_ADDR      0xE8000000UL
     #define FLASH_BASE_PHYS_HIGH 0x0ULL
     #define FLASH_LAW_SIZE       LAW_SIZE_128MB

hal/nxp_t2080.c

@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 #include <stdint.h>
-#include <string.h>
 #include "target.h"
 #include "printf.h"
 #include "image.h" /* for RAMFUNCTION */
@@ -374,59 +373,105 @@ static void hal_cpld_init(void)
 }
 
 #ifdef ENABLE_DDR
-/* Relocate stack from CPC SRAM to DDR for more stack space.
- * Call this after DDR is initialized and verified working.
- * This allows signature verification (ECC P384) which needs ~20-30KB stack. */
-static void hal_relocate_stack_to_ddr(void)
+/* Release CPC SRAM back to L2 cache mode.
+ * Call after stack is relocated to DDR (done in boot_entry_C).
+ * This gives us the full 2MB CPC as L3 cache for better performance.
+ *
+ * Before releasing CPC SRAM, .ramcode (RAMFUNCTION) is copied to DDR
+ * and TLB9 is remapped: VA 0xF8F00000 -> PA DDR_RAMCODE_ADDR so that
+ * RAMFUNCTION code (memcpy, wolfBoot_start, etc.) continues to work. */
+static void hal_reconfigure_cpc_as_cache(void)
 {
-    uint32_t new_sp = DDR_STACK_TOP - 64; /* 64-byte alignment, room for frame */
+    volatile uint32_t *cpc_csr0 = (volatile uint32_t *)(CPC_BASE + CPCCSR0);
+    volatile uint32_t *cpc_srcr0 = (volatile uint32_t *)(CPC_BASE + CPCSRCR0);
+    uint32_t reg;
 
-    /* Zero the DDR stack area for clean operation */
-    memset((void*)DDR_STACK_BASE, 0, DDR_STACK_SIZE);
+    /* Linker symbols for .ramcode section boundaries */
+    extern unsigned int _start_ramcode;
+    extern unsigned int _end_ramcode;
+    uint32_t ramcode_size = (uint32_t)&_end_ramcode - (uint32_t)&_start_ramcode;
+
+    /* Step 1: Copy .ramcode from CPC SRAM to DDR.
+     * Must use volatile loop — memcpy itself is in .ramcode! */
+    if (ramcode_size > 0) {
+        volatile const uint32_t *src = (volatile const uint32_t *)&_start_ramcode;
+        volatile uint32_t *dst = (volatile uint32_t *)DDR_RAMCODE_ADDR;
+        volatile uint32_t *end = (volatile uint32_t *)(DDR_RAMCODE_ADDR +
+                                                        ramcode_size);
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+
+        /* Flush D-cache and invalidate I-cache for the DDR copy */
+        flush_cache(DDR_RAMCODE_ADDR, ramcode_size);
 
-    /* Switch stack pointer from CPC SRAM to DDR.
-     * r1 is the stack pointer in PowerPC ABI. */
-    __asm__ __volatile__(
-        "mr 1, %0\n"         /* Move new stack address to r1 */
-        "sync\n"
-        :
-        : "r" (new_sp)
-        : "memory"
-    );
+        /* Step 2: Remap TLB9: same VA (0xF8F00000) -> DDR physical address.
+         * All .ramcode references use VA 0xF8F00000, so this makes them
+         * transparently access the DDR copy instead of CPC SRAM. */
+        set_tlb(1, 9,
+            L2SRAM_ADDR, DDR_RAMCODE_ADDR, 0,
+            MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
+            INITIAL_SRAM_BOOKE_SZ, 1);
+
+        /* Ensure TLB update and I-cache pick up new mapping */
+        invalidate_icache();
+    }
 
 #ifdef DEBUG_UART
-    wolfBoot_printf("Stack relocated to DDR (SP=0x%x)\n", new_sp);
+    wolfBoot_printf("Ramcode: copied %d bytes to DDR, TLB9 remapped\n",
+        ramcode_size);
 #endif
-}
-
-/* Release CPC SRAM back to L2 cache mode after stack is relocated to DDR.
- * This gives us the full 2MB CPC as instruction/data cache for better performance. */
-static void hal_reconfigure_cpc_as_cache(void)
-{
-    volatile uint32_t *cpc_csr0 = (volatile uint32_t *)(CPC_BASE + CPCCSR0);
-    volatile uint32_t *cpc_srcr0 = (volatile uint32_t *)(CPC_BASE + CPCSRCR0);
-    uint32_t reg;
 
-    /* Step 1: Flush the CPC to ensure no stale SRAM data.
-     * IMPORTANT: Read-modify-write to preserve CPCE/CPCPE enable bits! */
+    /* Step 3: Flush the CPC to push any dirty SRAM data out.
+     * Read-modify-write to preserve CPCE/CPCPE enable bits. */
     reg = *cpc_csr0;
     reg |= CPCCSR0_CPCFL;
     *cpc_csr0 = reg;
     __asm__ __volatile__("sync; isync" ::: "memory");
 
-    /* Step 2: Poll until flush completes (CPCFL clears) */
-    do {
-        reg = *cpc_csr0;
-    } while (reg & CPCCSR0_CPCFL);
+    /* Step 4: Poll until flush completes (CPCFL clears) */
+    while (*cpc_csr0 & CPCCSR0_CPCFL);
 
-    /* Step 3: Disable SRAM mode - release ways back to cache */
-    *cpc_srcr0 = 0;  /* Clear SRAMEN and SRAMSZ */
+    /* Step 5: Disable SRAM mode - release all ways back to cache */
+    *cpc_srcr0 = 0;
     __asm__ __volatile__("sync; isync" ::: "memory");
 
-    /* CPC remains enabled (CPCE/CPCPE preserved), now with all ways as cache */
+    /* Step 6: Disable CPC SRAM LAW (no longer needed — TLB9 now routes
+     * to DDR via LAW4, not CPC SRAM via LAW2).
+     * Keep TLB9 — it's remapped to DDR and still in use. */
+    set32(LAWAR(2), 0);
+
+    /* Step 7: Flash invalidate CPC to start fresh as cache */
+    reg = *cpc_csr0;
+    reg |= CPCCSR0_CPCFI;
+    *cpc_csr0 = reg;
+    __asm__ __volatile__("sync; isync" ::: "memory");
+    while (*cpc_csr0 & CPCCSR0_CPCFI);
+
+    /* CPC remains enabled (CPCE/CPCPE preserved), now all 2MB as cache */
 
 #ifdef DEBUG_UART
-    wolfBoot_printf("CPC: Released SRAM, full L2 cache enabled\n");
+    wolfBoot_printf("CPC: Released SRAM, full 2MB L2 cache enabled\n");
+#endif
+}
+
+/* Make flash TLB cacheable for XIP code performance.
+ * Changes TLB Entry 2 (flash) from MAS2_I|MAS2_G to MAS2_M.
+ * This enables L1 I-cache + L2 + CPC to cache flash instructions. */
+static void hal_flash_enable_caching(void)
+{
+    /* Rewrite flash TLB entry with cacheable attributes.
+     * MAS2_M = memory coherent, enables caching */
+    set_tlb(1, 2,
+        FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
+        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
+        FLASH_TLB_PAGESZ, 1);
+
+    /* Invalidate L1 I-cache so new TLB attributes take effect */
+    invalidate_icache();
+
+#ifdef DEBUG_UART
+    wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n");
 #endif
 }
 #endif /* ENABLE_DDR */
@@ -594,22 +639,17 @@ void hal_init(void)
 #ifdef DEBUG_UART
     hal_ddr_test();
 #endif
-    /* TODO: Implement proper assembly-based stack relocation to DDR.
-     * The current C-based approach corrupts return addresses because:
-     * 1. hal_init's return address is saved on CPC SRAM stack
-     * 2. Stack switch changes SP to DDR (zeroed area)
-     * 3. CPC release makes old stack contents invalid
-     * 4. Function returns read garbage addresses
+
+    /* Stack is already in DDR (relocated in boot_entry_C via
+     * ddr_call_with_stack trampoline before main() was called).
      *
-     * For now, keep using CPC SRAM stack (1MB should be enough for P384).
-     * Stack relocation needs to be done in assembly with proper LR handling.
-     */
-#if 0 /* Disabled until proper assembly implementation */
-    {
-        hal_relocate_stack_to_ddr();
-        hal_reconfigure_cpc_as_cache();
-    }
-#endif
+     * Now release CPC SRAM back to L2 cache and enable flash caching.
+     * This dramatically improves ECC signature verification performance:
+     * - CPC (2MB) becomes L3 cache for all memory accesses
+     * - Flash code is cached by L1 I-cache + L2 + CPC
+     * - Stack/data in DDR is cached by L1 D-cache + L2 + CPC */
+    hal_reconfigure_cpc_as_cache();
+    hal_flash_enable_caching();
 #endif
 }
 

src/boot_ppc.c

@@ -179,7 +179,25 @@ void boot_entry_C(void)
     }
 
     /* Run wolfBoot! */
+#ifdef ENABLE_DDR
+    /* DDR is initialized, .data and .bss are set up.
+     * Switch stack from CPC SRAM to DDR for:
+     * 1. Better performance (DDR stack is cacheable by L1/L2/CPC)
+     * 2. More stack space (64KB vs shared CPC SRAM)
+     * Uses assembly trampoline since we can't return after stack switch.
+     * The CPC SRAM will be released back to L2 cache in hal_init(). */
+    {
+        extern void ddr_call_with_stack(uint32_t func, uint32_t sp);
+        /* Zero DDR stack area using volatile to prevent memset transform */
+        volatile uint32_t *p = (volatile uint32_t *)DDR_STACK_BASE;
+        volatile uint32_t *e = (volatile uint32_t *)DDR_STACK_TOP;
+        while (p < e) { *p++ = 0; }
+        ddr_call_with_stack((uint32_t)main, DDR_STACK_TOP - 64);
+        /* Does not return */
+    }
+#else
     main();
+#endif
 }
 
 #ifndef BUILD_LOADER_STAGE1

src/boot_ppc_start.S

@@ -1001,6 +1001,30 @@ dcache_disable:
         blr
 #endif
 
+/* void ddr_call_with_stack(uint32_t func_ptr, uint32_t new_sp)
+ * Switches stack pointer to DDR and calls the given function.
+ * Used by boot_entry_C to transition from CPC SRAM stack to DDR stack
+ * before calling main(). Does not return.
+ * r3 = function pointer to call
+ * r4 = new stack pointer (top of DDR stack area) */
+.global ddr_call_with_stack
+ddr_call_with_stack:
+        mr      r1, r4          /* Set stack pointer to DDR */
+        /* Create minimal PPC ABI stack frame with terminated back chain */
+        li      r0, 0
+        stwu    r0, -4(r1)     /* Terminate back chain */
+        stwu    r0, -4(r1)
+        stwu    r1, -8(r1)    /* Save back chain and move SP */
+        lis     r0,     RESET_VECTOR@h
+        ori     r0, r0, RESET_VECTOR@l
+        stwu    r1, -8(r1)    /* Save back chain and move SP */
+        stw     r0, +12(r1)   /* Save return addr (underflow vector) */
+        /* Call the function */
+        mtctr   r3
+        bctrl
+        /* Should never reach here */
+1:      b       1b
+
 #ifdef USE_GOT
 
 /* function to relocate code, handling cache flushing and continue to