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dgarskedanielinux
dgarske
authored and
danielinux
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Add NXP S32K1xx support with full update functionality
- HAL: Flash (FTFC), UART (LPUART1), Clock (FIRC 48MHz), Watchdog - Requires NVM_FLASH_WRITEONCE=1 and RAM_CODE=1 for proper operation - Test app with interactive console: status, trigger, success, reboot - LED indicators: Green (v1), Blue (v2+) - Flash automation script: tools/scripts/nxp-s32k142-flash.sh - Tested on S32K142EVB with sector swap update Supported variants: S32K142 (256KB), S32K144 (512KB), S32K146 (1MB), S32K148 (2MB)
1 parent 8a04871 commit 4e3e55d

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‎.github/workflows/test-configs.yml‎

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arch: arm
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config-file: ./config/examples/mcxw-tz.config
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nxp_s32k142_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/nxp-s32k142.config
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nxp_s32k144_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/nxp-s32k144.config
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nxp_s32k146_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/nxp-s32k146.config
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nxp_s32k148_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/nxp-s32k148.config
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microchip_mpfs250_test:
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uses: ./.github/workflows/test-build-riscv.yml
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with:

‎.gitignore‎

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*.rom
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*.bin
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*.efi
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*.srec
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# Debug files
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*.dSYM/

‎Makefile‎

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$(WOLFBOOT_ORIGIN) wolfboot.bin \
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$(WOLFBOOT_PARTITION_BOOT_ADDRESS) test-app/image_v1_signed.bin
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factory.srec: factory.bin
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@echo "\t[BIN2SREC] $@"
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$(Q)$(OBJCOPY) -I binary -O srec --change-addresses=$(WOLFBOOT_ORIGIN) $< $@
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factory_wstage1.bin: $(BINASSEMBLE) stage1/loader_stage1.bin wolfboot.bin $(BOOT_IMG) $(PRIVATE_KEY) test-app/image_v1_signed.bin
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@echo "\t[MERGE] $@"
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$(Q)$(BINASSEMBLE) $@ \
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hex: wolfboot.hex
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srec: wolfboot.srec
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factory-srec: factory.srec
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%.hex:%.elf
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@echo "\t[ELF2HEX] $@"
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$(Q)rm -f src/wc_secure_calls.o
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$(Q)rm -f $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/*.o $(WOLFBOOT_LIB_WOLFTPM)/src/*.o $(WOLFBOOT_LIB_WOLFTPM)/hal/*.o $(WOLFBOOT_LIB_WOLFTPM)/examples/pcr/*.o
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$(Q)rm -f $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/Renesas/*.o
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$(Q)rm -f wolfboot.bin wolfboot.elf wolfboot.map test-update.rom wolfboot.hex
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$(Q)rm -f wolfboot.bin wolfboot.elf wolfboot.map test-update.rom wolfboot.hex wolfboot.srec factory.srec
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$(Q)rm -f $(MACHINE_OBJ) $(MAIN_TARGET) $(LSCRIPT)
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$(Q)rm -f $(OBJS)
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$(Q)rm -f tools/keytools/otp/otp-keystore-gen

‎config/examples/nxp-s32k142.config‎

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# wolfBoot configuration for NXP S32K142
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#
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# S32K142: Cortex-M4F, 256KB Flash, 32KB SRAM
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# Flash sector size: 2KB
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# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
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#
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# Build: cp config/examples/nxp-s32k142.config .config && make
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ARCH?=ARM
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CORTEX_M4?=1
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NO_MPU=1
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TARGET?=s32k1xx
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SIGN?=ECC256
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HASH?=SHA256
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# S32K1xx flash requires erase before write (cannot re-program same location)
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# This is required for sector swap trailer flag updates to work correctly
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# 2KB sectors (S32K142 only - larger variants use 4KB sectors)
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WOLFBOOT_SECTOR_SIZE?=0x800
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# Memory layout for S32K142 (256KB Flash):
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# Bootloader: 0x00000000 - 0x0000BFFF (48 KB)
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# Boot Partition: 0x0000C000 - 0x00024FFF (100 KB)
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# Update Partition: 0x00025000 - 0x0003DFFF (100 KB)
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# Swap Sector: 0x0003E000 - 0x0003E7FF (2 KB)
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WOLFBOOT_PARTITION_SIZE?=0x19000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x25000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x3E000
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# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
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# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
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#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN
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# Optionally enable watchdog
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#CFLAGS_EXTRA+=-DWATCHDOG
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# Debugging options (uncomment as needed)
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DEBUG?=0
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DEBUG_SYMBOLS?=0
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DEBUG_UART?=0
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT

‎config/examples/nxp-s32k144.config‎

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# wolfBoot configuration for NXP S32K144
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#
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# S32K144: Cortex-M4F, 512KB Flash, 64KB SRAM
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# Flash sector size: 4KB (larger flash variants use 4KB sectors)
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# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
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#
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# Build: cp config/examples/nxp-s32k144.config .config && make
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ARCH?=ARM
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CORTEX_M4?=1
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NO_MPU=1
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TARGET?=s32k1xx
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SIGN?=ECC256
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HASH?=SHA256
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# S32K1xx flash requires erase before write (cannot re-program same location)
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# This is required for sector swap trailer flag updates to work correctly
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Select S32K144 variant for correct flash size and sector size
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CFLAGS_EXTRA+=-DS32K144
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# 4KB sectors (S32K144/146/148 with 512KB+ flash)
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WOLFBOOT_SECTOR_SIZE?=0x1000
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# Memory layout for S32K144 (512KB Flash):
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# Bootloader: 0x00000000 - 0x0000BFFF (48 KB)
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# Boot Partition: 0x0000C000 - 0x00043FFF (224 KB)
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# Update Partition: 0x00044000 - 0x0007BFFF (224 KB)
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# Swap Sector: 0x0007C000 - 0x0007CFFF (4 KB)
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WOLFBOOT_PARTITION_SIZE?=0x38000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x44000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x7C000
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# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
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# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
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#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN
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# Optionally enable watchdog
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#CFLAGS_EXTRA+=-DWATCHDOG
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# Debugging options (uncomment as needed)
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DEBUG?=0
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DEBUG_SYMBOLS?=0
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DEBUG_UART?=0
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT

‎config/examples/nxp-s32k146.config‎

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# wolfBoot configuration for NXP S32K146
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#
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# S32K146: Cortex-M4F, 1MB Flash, 128KB SRAM
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# Flash sector size: 4KB (larger flash variants use 4KB sectors)
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# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
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#
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# Build: cp config/examples/nxp-s32k146.config .config && make
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ARCH?=ARM
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CORTEX_M4?=1
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NO_MPU=1
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TARGET?=s32k1xx
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SIGN?=ECC256
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HASH?=SHA256
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# S32K1xx flash requires erase before write (cannot re-program same location)
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# This is required for sector swap trailer flag updates to work correctly
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Select S32K146 variant for correct flash size and sector size
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CFLAGS_EXTRA+=-DS32K146
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# 4KB sectors (S32K144/146/148 with 512KB+ flash)
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WOLFBOOT_SECTOR_SIZE?=0x1000
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# Memory layout for S32K146 (1MB Flash):
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# Bootloader: 0x00000000 - 0x0000BFFF (48 KB)
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# Boot Partition: 0x0000C000 - 0x0007FFFF (464 KB)
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# Update Partition: 0x00080000 - 0x000F3FFF (464 KB)
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# Swap Sector: 0x000F4000 - 0x000F4FFF (4 KB)
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WOLFBOOT_PARTITION_SIZE?=0x74000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x80000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xF4000
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# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
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# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
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#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN
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# Optionally enable watchdog
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#CFLAGS_EXTRA+=-DWATCHDOG
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# Debugging options (uncomment as needed)
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DEBUG?=0
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DEBUG_SYMBOLS?=0
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DEBUG_UART?=0
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT

‎config/examples/nxp-s32k148.config‎

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# wolfBoot configuration for NXP S32K148
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#
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# S32K148: Cortex-M4F, 2MB Flash, 256KB SRAM
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# Flash sector size: 4KB (larger flash variants use 4KB sectors)
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# Default: RUN mode at 48 MHz (FIRC - internal RC oscillator)
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#
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# Build: cp config/examples/nxp-s32k148.config .config && make
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ARCH?=ARM
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CORTEX_M4?=1
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NO_MPU=1
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TARGET?=s32k1xx
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SIGN?=ECC256
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HASH?=SHA256
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VTOR?=1
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NO_ASM?=0
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EXT_FLASH?=0
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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# S32K1xx flash requires erase before write (cannot re-program same location)
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# This is required for sector swap trailer flag updates to work correctly
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NVM_FLASH_WRITEONCE?=1
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WOLFBOOT_VERSION?=0
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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DUALBANK_SWAP?=0
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# Select S32K148 variant for correct flash size and sector size
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CFLAGS_EXTRA+=-DS32K148
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# 4KB sectors (S32K144/146/148 with 512KB+ flash)
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WOLFBOOT_SECTOR_SIZE?=0x1000
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# Memory layout for S32K148 (2MB Flash):
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# Bootloader: 0x00000000 - 0x0000BFFF (48 KB)
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# Boot Partition: 0x0000C000 - 0x000FBFFF (960 KB)
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# Update Partition: 0x000FC000 - 0x001EBFFF (960 KB)
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# Swap Sector: 0x001EC000 - 0x001ECFFF (4 KB)
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WOLFBOOT_PARTITION_SIZE?=0xF0000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xC000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xFC000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x1EC000
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# Clock mode: Default is RUN mode with FIRC (48 MHz internal RC)
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# To enable HSRUN mode (112 MHz), uncomment below (requires SOSC + SPLL, not fully implemented):
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#CFLAGS_EXTRA+=-DS32K1XX_CLOCK_HSRUN
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# Optionally enable watchdog
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#CFLAGS_EXTRA+=-DWATCHDOG
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# Debugging options (uncomment as needed)
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DEBUG?=0
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DEBUG_SYMBOLS?=0
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DEBUG_UART?=0
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#CFLAGS_EXTRA+=-DDEBUG_HARDFAULT

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