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‎docs/Targets.md‎

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@@ -802,7 +802,8 @@ The PolarFire SoC is a 64-bit RISC-V SoC featuring a five-core CPU cluster (1×
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`hal/mpfs250.ld` - Linker script for S-mode (HSS-based boot)
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`hal/mpfs250-m.ld` - Linker script for M-mode (eNVM + L2 SRAM)
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`hal/mpfs.dts` - Device tree source
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`hal/mpfs.yaml` - HSS payload generator configuration
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`hal/mpfs.yaml` - HSS payload generator configuration for use of DDR
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`hal/mpfs-l2lim.yaml` - HSS payload generator for the use of L2-LIM
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`hal/mpfs250.its` - Example FIT image creation template
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### PolarFire SoC Building wolfBoot
@@ -906,25 +907,49 @@ Notes:
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### PolarFire SoC M-Mode (bare-metal eNVM boot)
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In M-Mode wolfBoot runs directly on the E51 monitor core from eNVM — no HSS required. The signed
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application is loaded from SC QSPI flash into L2 Scratchpad (on-chip RAM). This is the simplest
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bring-up path.
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wolfBoot supports running directly in Machine Mode (M-mode) on PolarFire SoC, replacing the Hart
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Software Services (HSS) as the first-stage bootloader. wolfBoot runs on the E51 monitor core from
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eNVM and loads a signed application from SC QSPI flash into L2 Scratchpad (on-chip RAM) — no HSS
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or DDR required. This is the simplest bring-up path.
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**Features:**
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* Runs on E51 monitor core (hart 0) directly from eNVM
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* Executes from L2 Scratchpad SRAM (256 KB at `0x0A000000`)
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* Loads signed application from SC QSPI flash to L2 Scratchpad (`0x0A010200`)
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* No HSS or DDR required — boots entirely from on-chip memory
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* Wakes and manages secondary U54 harts via IPI
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* Per-hart UART output (each hart uses its own MMUART)
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* ECC384 + SHA384 signature verification
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**Relevant files:**
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| File | Description |
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|------|-------------|
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| `config/examples/polarfire_mpfs250_m_qspi.config` | M-mode + SC QSPI configuration |
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| `hal/mpfs250-m.ld` | M-mode linker script (eNVM + L2 SRAM) |
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| `hal/mpfs250.c` | HAL with QSPI driver, UART, L2 cache init |
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| `src/boot_riscv_start.S` | M-mode assembly startup |
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**Boot flow:**
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1. CPU starts at eNVM reset vector (`0x20220100`)
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2. Startup code copies wolfBoot to L2 Scratchpad (`0x0A000000`) and jumps there
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3. wolfBoot reads the signed image from QSPI flash into L2 Scratchpad (`0x0A010200`)
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4. Signature is verified, then execution jumps to the application
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1. **eNVM reset vector** (`0x20220100`): CPU starts, startup code copies wolfBoot to L2 Scratchpad
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2. **L2 Scratchpad execution** (`0x0A000000`): wolfBoot runs from scratchpad
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3. **Hardware init**: L2 cache configuration, UART setup
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4. **QSPI init**: SC QSPI controller (`0x37020100`), JEDEC ID read, 4-byte address mode
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5. **Image load**: Read signed image from QSPI flash (`0x20000`) to L2 Scratchpad (`0x0A010200`)
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6. **Verify & boot**: SHA384 integrity check, ECC384 signature verification, jump to app
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**Build:**
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```sh
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cp config/examples/polarfire_mpfs250_m_qspi.config .config
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make clean && make wolfboot.elf
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```
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**Flash wolfBoot to eNVM** (requires SmartDesign / SmartFusion2 Libero SoC install):
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**Flash wolfBoot to eNVM** (requires SoftConsole / Libero SoC install):
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```sh
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java -jar $SC_INSTALL_DIR/extras/mpfs/mpfsBootmodeProgrammer.jar \
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export SC_INSTALL_DIR=/opt/Microchip/SoftConsole-v2022.2-RISC-V-747
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$SC_INSTALL_DIR/eclipse/jre/bin/java -jar \
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$SC_INSTALL_DIR/extras/mpfs/mpfsBootmodeProgrammer.jar \
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--bootmode 1 --die MPFS250T --package FCG1152 --workdir $PWD wolfboot.elf
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```
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@@ -946,7 +971,25 @@ The script:
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3. Transfers the binary in 256-byte ACK-driven chunks
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4. wolfBoot erases, writes, and then continues booting the new image
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Use `0x20000` for the boot partition and `0x2000000` for the update partition.
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Use `0x20000` for the boot partition and `0x02000000` for the update partition.
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**QSPI partition layout** (Micron MT25QL01G, 128 MB):
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| Region | Address | Size |
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|--------|---------|------|
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| Boot partition | `0x00020000` | ~32 MB |
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| Update partition | `0x02000000` | ~32 MB |
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| Swap partition | `0x04000000` | 64 KB |
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**UART mapping:**
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| Hart | Core | MMUART | USB device |
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|------|------|--------|------------|
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| 0 | E51 | MMUART0 | /dev/ttyUSB0 |
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| 1 | U54_1 | MMUART1 | /dev/ttyUSB1 |
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| 2 | U54_2 | MMUART2 | N/A |
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| 3 | U54_3 | MMUART3 | N/A |
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| 4 | U54_4 | MMUART4 | N/A |
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**Expected serial output on successful boot:**
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```
@@ -963,21 +1006,25 @@ Booting at 0x...
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```
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**Notes:**
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- The E51 is `rv64imac`; the `rdtime` CSR instruction is not available in bare-metal M-mode.
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wolfBoot uses a calibrated busy-loop for all delays (`udelay()` in `hal/mpfs250.c`).
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- The E51 is `rv64imac` (no FPU or crypto extensions). wolfBoot is compiled with `NO_ASM=1` to
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use portable C crypto implementations and `-march=rv64imac -mabi=lp64` for correct code
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generation. The `rdtime` CSR instruction is not available in bare-metal M-mode; wolfBoot uses a
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calibrated busy-loop for all delays (`udelay()` in `hal/mpfs250.c`).
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- `UART_QSPI_PROGRAM=1` adds a 3-second boot pause every time. Set to `0` once the flash
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contents are stable.
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- The config uses `WOLFBOOT_LOAD_ADDRESS=0x0A010200` to place the application in L2 Scratchpad
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above wolfBoot code (~64KB at `0x0A000000`), with the stack at the top of the 256KB region.
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- **LIM instruction fetch limitation:** The on-chip LIM (`0x08000000`, 2MB) is backed by L2
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cache ways. When `L2_WAY_ENABLE` is set to `0x0B` (all cache ways 0-7 active for caching),
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above wolfBoot code (~64 KB at `0x0A000000`), with the stack at the top of the 256 KB region.
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- **LIM instruction fetch limitation:** The on-chip LIM (`0x08000000`, 2 MB) is backed by L2
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cache ways. When `L2_WAY_ENABLE` is set to `0x0B` (all cache ways 0–7 active for caching),
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no ways remain for LIM backing SRAM. Data reads from LIM work through the L2 cache, but
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instruction fetch silently hangs — the CPU stalls with no trap generated. For this reason the
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application is loaded into L2 Scratchpad (`0x0A000000`), which is always accessible regardless
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of `L2_WAY_ENABLE`. To use LIM, reduce `L2_WAY_ENABLE` to free cache ways for LIM backing.
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- **Strip debug symbols** before signing the test-app ELF. The debug build is ~150KB but the
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stripped ELF is ~5KB. L2 Scratchpad has ~150KB available between wolfBoot code and the stack:
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- **Strip debug symbols** before signing the test-app ELF. The debug build is ~150 KB but the
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stripped ELF is ~5 KB. L2 Scratchpad has ~150 KB available between wolfBoot code and the stack:
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`riscv64-unknown-elf-strip --strip-debug test-app/image.elf`
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- **DDR support:** DDR initialization is available on the `polarfire_ddr` branch for use cases
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that require loading larger applications to DDR memory.
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### PolarFire testing
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@@ -1439,108 +1486,6 @@ ML-DSA 87 verify 200 ops took 1.077 sec, avg 5.385 ms, 185.704 ops/
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Benchmark complete
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```
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### PolarFire Machine Mode (M-Mode) Support
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wolfBoot supports running directly in Machine Mode (M-mode) on PolarFire SoC,
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replacing the Hart Software Services (HSS) as the first-stage bootloader. In
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M-mode, wolfBoot runs on the E51 monitor core and loads a signed application
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from SC QSPI flash to L2 Scratchpad SRAM. LIM is not used as an execute region
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due to instruction-fetch limitations (see note below).
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#### M-Mode Features
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* Runs on E51 monitor core (hart 0) directly from eNVM
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* Executes from L2 Scratchpad SRAM (256KB at 0x0A000000)
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* Loads signed application from SC QSPI flash to L2 Scratchpad (0x0A010200)
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* No HSS or DDR required — boots entirely from on-chip memory
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* Wakes and manages secondary U54 harts via IPI
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* Per-hart UART output (each hart uses its own MMUART)
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* ECC384 + SHA384 signature verification
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#### M-Mode Files
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| File | Description |
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|------|-------------|
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| `config/examples/polarfire_mpfs250_m_qspi.config` | M-mode + SC QSPI configuration |
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| `hal/mpfs250-m.ld` | M-mode linker script (eNVM + L2 SRAM) |
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| `hal/mpfs250.c` | HAL with QSPI driver, UART, L2 cache init |
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| `src/boot_riscv_start.S` | M-mode assembly startup |
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#### Building for M-Mode
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```sh
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# Copy M-mode QSPI configuration
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cp config/examples/polarfire_mpfs250_m_qspi.config .config
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# Build wolfBoot and signed test-app
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make clean
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make
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```
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This produces:
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- `wolfboot.elf` — bootloader for eNVM (~26KB)
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- `test-app/image_v1_signed.bin` — signed application for QSPI flash
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#### Flashing
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M-mode requires programming two targets:
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1. **eNVM** (wolfBoot): Programmed via JTAG using mpfsBootmodeProgrammer (bootmode 1)
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2. **QSPI flash** (signed application): Programmed via Libero/FPExpress SPI programming
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```sh
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# Set SoftConsole installation directory
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export SC_INSTALL_DIR=/opt/Microchip/SoftConsole-v2022.2-RISC-V-747
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# Flash wolfboot.elf to eNVM
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$SC_INSTALL_DIR/eclipse/jre/bin/java -jar \
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$SC_INSTALL_DIR/extras/mpfs/mpfsBootmodeProgrammer.jar \
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--bootmode 1 --die MPFS250T --package FCG1152 --workdir $PWD wolfboot.elf
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# Flash test-app/image_v1_signed.bin to QSPI at offset 0x20000
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# (use Libero SoC Design Suite SPI flash programming)
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```
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#### M-Mode Boot Flow
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1. **eNVM Reset Vector** (0x20220100): CPU starts, copies code to L2 SRAM
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2. **L2 SRAM Execution** (0x0A000000): wolfBoot runs from scratchpad
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3. **Hardware Init**: L2 cache configuration, UART setup
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4. **QSPI Init**: SC QSPI controller (0x37020100), JEDEC ID read, 4-byte address mode
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5. **Image Load**: Read signed image from QSPI flash (0x20000) to L2 Scratchpad (0x0A010200)
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6. **Verify & Boot**: SHA384 integrity check, ECC384 signature verification, jump to app
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#### M-Mode QSPI Partition Layout
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The SC QSPI flash (Micron MT25QL01G, 128MB) is partitioned as:
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| Region | Address | Size |
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|--------|---------|------|
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| Boot partition | 0x00020000 | ~32MB |
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| Update partition | 0x02000000 | ~32MB |
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| Swap partition | 0x04000000 | 64KB |
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#### M-Mode UART Mapping
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| Hart | Core | MMUART | USB Device |
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|------|------|--------|------------|
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| 0 | E51 | MMUART0 | /dev/ttyUSB0 |
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| 1 | U54_1 | MMUART1 | /dev/ttyUSB1 |
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| 2 | U54_2 | MMUART2 | N/A |
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| 3 | U54_3 | MMUART3 | N/A |
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| 4 | U54_4 | MMUART4 | N/A |
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#### M-Mode Notes
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1535-
* The E51 core is rv64imac (no FPU or crypto extensions). wolfBoot is compiled
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with `NO_ASM=1` to use portable C crypto implementations and
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`-march=rv64imac -mabi=lp64` for correct code generation.
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* CLINT MTIME counter is not running in bare-metal M-mode (no HSS), so
1539-
`udelay()` uses a calibrated busy loop instead of the timer CSR.
1540-
* DDR initialization support is available on the `polarfire_ddr` branch for
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use cases that require loading larger applications to DDR memory.
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1543-
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## STM32F7
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The STM32-F76x and F77x offer dual-bank hardware-assisted swapping.

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