Skip to content

Commit 1fe4557

Browse files
danielinuxdanielinux
committed
Fixes for stm32u5, added workflow test
1 parent d06414e commit 1fe4557

6 files changed

Lines changed: 121 additions & 45 deletions

File tree

.github/workflows/emu-test-stm32h5.yml renamed to .github/workflows/trustzone-emulator-tests.yml

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
name: emu-test-stm32h5
1+
name: trustzone-emulator-tests
22

33
on:
44
push:
55
pull_request:
66

77
jobs:
8-
emu-test-stm32h5:
8+
trustzone-emulator-tests:
99
runs-on: ubuntu-latest
1010
container:
1111
image: ghcr.io/danielinux/m33mu-ci:testing
@@ -26,3 +26,14 @@ jobs:
2626
working-directory: test-app/emu-test-apps
2727
run: |
2828
SCENARIOS=C ./test.sh
29+
30+
- name: Clean and build stm32u5 (TZ + wolfcrypt)
31+
run: |
32+
make clean distclean
33+
cp config/examples/stm32u5-wolfcrypt-tz.config .config
34+
make wolfboot.bin
35+
36+
- name: Run emu test (stm32u5)
37+
working-directory: test-app/emu-test-apps
38+
run: |
39+
TARGET=stm32u5 ./test.sh

‎hal/stm32_tz.c‎

Lines changed: 33 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
#include "hal/stm32u5.h"
3030
#endif
3131

32-
#ifdef TARGET_stm32h5
32+
#if defined(TARGET_stm32h5)
3333
#include "hal/stm32h5.h"
3434
#endif
3535

@@ -225,6 +225,38 @@ void hal_gtzc_init(void)
225225
}
226226
}
227227

228+
#elif defined(TARGET_stm32u5)
229+
230+
#define GTZC_MPCBB1_S_BASE (0x50032C00)
231+
#define GTZC_MPCBB1_S_VCTR_BASE (GTZC_MPCBB1_S_BASE + 0x100)
232+
233+
#define GTZC_MPCBB2_S_BASE (0x50033000)
234+
#define GTZC_MPCBB2_S_VCTR_BASE (GTZC_MPCBB2_S_BASE + 0x100)
235+
236+
#define SET_GTZC_MPCBBx_S_VCTR(bank,n,val) \
237+
(*((volatile uint32_t *)(GTZC_MPCBB##bank##_S_VCTR_BASE ) + n ))= val
238+
239+
void hal_gtzc_init(void)
240+
{
241+
int i;
242+
/* One bit in the bitmask: 512B (STM32U5) */
243+
244+
/* Configure SRAM1 lower 128 KB as secure (0x20000000 - 0x2001FFFF). */
245+
for (i = 0; i < 8; i++) {
246+
SET_GTZC_MPCBBx_S_VCTR(1, i, 0xFFFFFFFF);
247+
}
248+
249+
/* Configure SRAM1 upper 128 KB as non-secure (0x20020000 - 0x2003FFFF). */
250+
for (i = 8; i < 16; i++) {
251+
SET_GTZC_MPCBBx_S_VCTR(1, i, 0x0);
252+
}
253+
254+
/* Configure SRAM2 as non-secure (0x20030000 - 0x2003FFFF). */
255+
for (i = 0; i < 4; i++) {
256+
SET_GTZC_MPCBBx_S_VCTR(2, i, 0x0);
257+
}
258+
}
259+
228260
#else
229261

230262
#define GTZC_MPCBB1_S_BASE (0x50032C00)

‎hal/stm32u5.c‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,35 @@ static void led_unsecure()
489489
#endif
490490
}
491491

492+
#if TZ_SECURE()
493+
#define TZSC1_BASE 0x50032400u
494+
#define TZSC_SECCFGR1 (*(volatile uint32_t *)(TZSC1_BASE + 0x10u))
495+
#define TZSC_SECCFGR1_USART3SEC (1u << 10)
496+
497+
static void periph_unsecure(void)
498+
{
499+
volatile uint32_t reg;
500+
501+
/* Enable clock for GPIO D (USART3 pins PD8/PD9) */
502+
RCC_AHB2ENR1_CLOCK_ER |= GPIOD_AHB2ENR1_CLOCK_ER;
503+
504+
/* Enable clock for USART3 */
505+
RCC_APB1LENR |= (1u << 18);
506+
507+
/* Unsecure USART3 pins (PD8 TX, PD9 RX) */
508+
GPIOD_SECCFGR &= ~(1u << 8);
509+
GPIOD_SECCFGR &= ~(1u << 9);
510+
511+
/* Unsecure USART3 peripheral in GTZC TZSC */
512+
reg = TZSC_SECCFGR1;
513+
if (reg & TZSC_SECCFGR1_USART3SEC) {
514+
reg &= ~TZSC_SECCFGR1_USART3SEC;
515+
DMB();
516+
TZSC_SECCFGR1 = reg;
517+
}
518+
}
519+
#endif
520+
492521
#if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
493522
static uint8_t bootloader_copy_mem[BOOTLOADER_SIZE];
494523
static void RAMFUNCTION fork_bootloader(void)
@@ -530,6 +559,7 @@ void hal_prepare_boot(void)
530559
clock_pll_off();
531560
#endif
532561
#if TZ_SECURE()
562+
periph_unsecure();
533563
led_unsecure();
534564
#endif
535565
}

‎hal/stm32u5.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@
119119

120120
#define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */
121121
#define RCC_AHB3ENR_GTZC2EN (1 << 12)
122+
123+
#define RCC_APB1LENR (*(volatile uint32_t *)(RCC_BASE + 0x9C)) /* RM0456 - Table 108 */
122124
#define RCC_AHB3ENR_PWREN (1 << 2)
123125

124126
#define RCC_ICSCR1 (*(volatile uint32_t *)(RCC_BASE + 0x08))
@@ -249,10 +251,12 @@
249251

250252
/* GPIO*/
251253
#define GPIOC_BASE 0x52020800
254+
#define GPIOD_BASE 0x52020C00
252255
#define GPIOG_BASE 0x52021800
253256
#define GPIOH_BASE 0x52021C00
254257

255258
#define GPIOC_SECCFGR (*(volatile uint32_t *)(GPIOC_BASE + 0x30))
259+
#define GPIOD_SECCFGR (*(volatile uint32_t *)(GPIOD_BASE + 0x30))
256260
#define GPIOG_SECCFGR (*(volatile uint32_t *)(GPIOG_BASE + 0x30))
257261
#define GPIOH_SECCFGR (*(volatile uint32_t *)(GPIOH_BASE + 0x30))
258262

@@ -266,6 +270,7 @@
266270

267271
#define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
268272
#define GPIOC_AHB2ENR1_CLOCK_ER (1 << 2)
273+
#define GPIOD_AHB2ENR1_CLOCK_ER (1 << 3)
269274
#define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
270275
#define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7)
271276
#define TRNG_AHB2_CLOCK_ER (1 << 18)

‎test-app/emu-test-apps/stm32u585/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,14 @@
11
CC=arm-none-eabi-gcc
22
OBJCOPY ?= arm-none-eabi-objcopy
33

4-
CFLAGS := -mcpu=cortex-m33 -mthumb -mcmse -Os -ffreestanding -fdata-sections -ffunction-sections -g -ggdb
4+
CFLAGS := -mcpu=cortex-m33 -mthumb -Os -ffreestanding -fdata-sections -ffunction-sections -g -ggdb
55
CFLAGS += -I. -I../common -I../../../include -DEMU_STM32
66
CFLAGS += -DIMAGE_HEADER_SIZE=$(IMAGE_HEADER_SIZE)
77
LDFLAGS := -nostdlib -T target.ld -Wl,-gc-sections
88
LDLIBS := -Wl,--start-group -lc -lm -lgcc -lnosys -Wl,--end-group
99
NSC_OBJ :=
1010
ifeq ($(TZEN),1)
11+
CFLAGS += -DNONSECURE_APP
1112
CFLAGS += -DWOLFCRYPT_SECURE_MODE
1213
NSC_OBJ := ../../../src/wc_secure_calls.o
1314
endif

‎test-app/emu-test-apps/stm32u585/target.ld‎

Lines changed: 38 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,61 @@
1-
/* Minimal linker script for STM32U585 memory map */
21
MEMORY
32
{
4-
FLASH (rx) : ORIGIN = 0x08000100, LENGTH = 0x001FFF00
5-
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x000C0000
3+
FLASH (rx) : ORIGIN = 0x8040100, LENGTH = 0x1f700
4+
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 128K
65
}
76

8-
_estack = ORIGIN(RAM) + LENGTH(RAM);
9-
_sidata = LOADADDR(.data);
10-
117
SECTIONS
128
{
13-
.isr_vector :
14-
{
15-
KEEP(*(.isr_vector))
16-
} > FLASH
17-
189
.text :
1910
{
11+
_start_text = .;
12+
. = ALIGN(8);
13+
KEEP(*(.isr_vector))
14+
. = ALIGN(8);
15+
*(.init)
16+
*(.fini)
2017
*(.text*)
2118
*(.rodata*)
22-
*(.ARM.extab* .gnu.linkonce.armextab.*)
23-
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
24-
*(.glue_7)
25-
*(.glue_7t)
26-
*(.eh_frame)
27-
} > FLASH
28-
29-
.preinit_array :
30-
{
31-
__preinit_array_start = .;
32-
KEEP(*(.preinit_array*))
33-
__preinit_array_end = .;
19+
. = ALIGN(8);
20+
_end_text = .;
3421
} > FLASH
3522

36-
.init_array :
23+
.edidx :
3724
{
38-
__init_array_start = .;
39-
KEEP(*(.init_array*))
40-
__init_array_end = .;
25+
. = ALIGN(4);
26+
*(.ARM.exidx*)
4127
} > FLASH
4228

43-
.fini_array :
44-
{
45-
__fini_array_start = .;
46-
KEEP(*(.fini_array*))
47-
__fini_array_end = .;
48-
} > FLASH
29+
_stored_data = .;
4930

50-
.data :
31+
.data : AT (_stored_data)
5132
{
52-
_sdata = .;
53-
*(.data*)
54-
_edata = .;
55-
} > RAM AT > FLASH
33+
_start_data = .;
34+
KEEP(*(.data*))
35+
. = ALIGN(8);
36+
KEEP(*(.ramcode))
37+
. = ALIGN(8);
38+
_end_data = .;
39+
} > RAM
5640

57-
.bss (NOLOAD) :
41+
.bss :
5842
{
59-
_sbss = .;
43+
_start_bss = .;
6044
*(.bss*)
6145
*(COMMON)
62-
_ebss = .;
46+
. = ALIGN(8);
47+
_end_bss = .;
48+
_end = .;
6349
} > RAM
6450
}
51+
52+
PROVIDE(_start_heap = _end);
53+
PROVIDE(_end_stack = ORIGIN(RAM) + LENGTH(RAM));
54+
55+
/* Emu app startup expects these symbols. */
56+
_estack = _end_stack;
57+
_sidata = _stored_data;
58+
_sdata = _start_data;
59+
_edata = _end_data;
60+
_sbss = _start_bss;
61+
_ebss = _end_bss;

0 commit comments

Comments
 (0)