Progress with getting XMODEM updates working.

Author: dgarske

hal/s32k1xx.c

@@ -28,6 +28,13 @@
 #include "hal.h"
 #include "printf.h"
 
+/* Override RAMFUNCTION for test-app: when RAM_CODE is set but not __WOLFBOOT,
+ * we still need flash functions to run from RAM for self-programming. */
+#if defined(RAM_CODE) && !defined(__WOLFBOOT)
+    #undef RAMFUNCTION
+    #define RAMFUNCTION __attribute__((used,section(".ramcode"),long_call))
+#endif
+
 /* Assembly helpers */
 #define DMB() __asm__ volatile ("dmb")
 #define DSB() __asm__ volatile ("dsb")
@@ -280,43 +287,47 @@ void uart_init(void)
     LPUART_CTRL = LPUART_CTRL_TE | LPUART_CTRL_RE;
 }
 
+/* Transmit a single byte (raw, no conversion) - RAMFUNCTION for use during flash ops */
+void RAMFUNCTION uart_tx(uint8_t byte)
+{
+    while (!(LPUART1_STAT & LPUART_STAT_TDRE)) {}
+    LPUART1_DATA = byte;
+    while (!(LPUART1_STAT & LPUART_STAT_TC)) {}
+}
+
+/* Used for sending ASCII and CRLF conversions */
 void uart_write(const char* buf, unsigned int sz)
 {
     unsigned int i;
-
     for (i = 0; i < sz; i++) {
         /* Handle newline -> CRLF conversion */
         if (buf[i] == '\n') {
-            /* Wait for transmit buffer empty */
-            while (!(LPUART_STAT & LPUART_STAT_TDRE)) {}
-            LPUART_DATA = '\r';
+            uart_tx('\r');
         }
-
-        /* Wait for transmit buffer empty */
-        while (!(LPUART_STAT & LPUART_STAT_TDRE)) {}
-        LPUART_DATA = buf[i];
+        uart_tx(buf[i]);
     }
 
     /* Wait for transmission complete */
     while (!(LPUART_STAT & LPUART_STAT_TC)) {}
 }
 
-/* Read a single character from UART (non-blocking)
- * Returns: 1 if character read, 0 if no data available, -1 on error
+
+
+/* Read a single character from UART (non-blocking) - RAMFUNCTION for use during flash ops
+ * Returns: 1 if character read, 0 if no data available
  */
-int uart_read(char* c)
+int RAMFUNCTION uart_read(char* c)
 {
-    uint32_t stat = LPUART_STAT;
+    uint32_t stat = LPUART1_STAT;
 
-    /* Clear any error flags */
+    /* Clear any error flags first */
     if (stat & (LPUART_STAT_OR | LPUART_STAT_NF | LPUART_STAT_FE | LPUART_STAT_PF)) {
-        LPUART_STAT = stat;  /* Write 1 to clear flags */
-        return -1;
+        LPUART1_STAT = stat;  /* Write 1 to clear flags */
     }
 
-    /* Check if data available */
+    /* Check if data available - read even if there was an error */
     if (stat & LPUART_STAT_RDRF) {
-        *c = (char)(LPUART_DATA & 0xFF);
+        *c = (char)(LPUART1_DATA & 0xFF);
         return 1;
     }
 

hal/s32k1xx.h

@@ -74,6 +74,29 @@
 #define CLOCK_SPEED         48000000UL
 #endif
 
+/* ============== NVIC - Nested Vectored Interrupt Controller ============== */
+#define NVIC_BASE           (0xE000E100UL)
+#define NVIC_ISER(n)        (*(volatile uint32_t *)(NVIC_BASE + 0x000UL + 4*(n)))  /* Interrupt Set Enable */
+#define NVIC_ICER(n)        (*(volatile uint32_t *)(NVIC_BASE + 0x080UL + 4*(n)))  /* Interrupt Clear Enable */
+#define NVIC_ISPR(n)        (*(volatile uint32_t *)(NVIC_BASE + 0x100UL + 4*(n)))  /* Interrupt Set Pending */
+#define NVIC_ICPR(n)        (*(volatile uint32_t *)(NVIC_BASE + 0x180UL + 4*(n)))  /* Interrupt Clear Pending */
+#define NVIC_IPR(n)         (*(volatile uint32_t *)(NVIC_BASE + 0x300UL + 4*(n)))  /* Interrupt Priority */
+
+/* S32K142 LPUART IRQ numbers */
+#define LPUART0_IRQn        31
+#define LPUART1_IRQn        33
+#define LPUART2_IRQn        35
+
+/* NVIC helper macros */
+#define NVIC_EnableIRQ(irq)     NVIC_ISER((irq) >> 5) = (1UL << ((irq) & 0x1F))
+#define NVIC_DisableIRQ(irq)    NVIC_ICER((irq) >> 5) = (1UL << ((irq) & 0x1F))
+#define NVIC_SetPriority(irq, prio)  \
+    do { \
+        uint32_t _idx = (irq) >> 2; \
+        uint32_t _shift = (((irq) & 0x3) << 3) + 4; \
+        NVIC_IPR(_idx) = (NVIC_IPR(_idx) & ~(0xFUL << _shift)) | (((prio) & 0xF) << _shift); \
+    } while(0)
+
 /* ============== System Control Registers ============== */
 
 /* SCG - System Clock Generator */