Attempt to fix RISC-V CI. Adding the MPFS test script.

Author: dgarske

.gdbinit

@@ -1,9 +1,6 @@
 file wolfboot.elf
 tar rem:3333
-add-symbol-file ../hart-software-services/build/hss-l2scratch.elf
+add-symbol-file test-app/image.elf
 set pagination off
 foc c
 
-set $target_riscv=1
-set mem inaccessible-by-default off
-set architecture riscv:rv64

.github/workflows/test-configs.yml

@@ -19,8 +19,7 @@ jobs:
     with:
       arch: riscv
       config-file: ./config/examples/hifive1.config
-      # Only building wolfBoot - not test app for now (cross compiler cannot find suitable multilib set for '-march=rv32imafdc_zicsr_zmmul_zaamo_zalrsc_zca_zcd_zcf'/'-mabi=ilp32d')
-      # Consider building cached RISCV64 toolchain for this target
+      # Only building wolfBoot (test-app needs freedom-e-sdk multilib for ilp32d)
       make-args: wolfboot.bin
 
   sama5d3_test:

.gitignore

@@ -327,6 +327,7 @@ language.settings.xml
 
 # PolarFire SoC Device Tree Binary
 hal/mpfs.dtb
+bootmode1/
 
 # Emulator test: generated linker scripts
 test-app/emu-test-apps/*/target.ld

arch.mk

@@ -563,30 +563,24 @@ endif
 ## RISCV (32-bit)
 ifeq ($(ARCH),RISCV)
   CROSS_COMPILE?=riscv32-unknown-elf-
-  # Detect zicsr/zifencei support: GCC 12+ may require these extensions
-  # explicitly. However, GCC 15 decomposes arch strings (m→zmmul,
-  # a→zaamo+zalrsc, c→zca) which can break multilib lookup.
-  # Verify with a link test, not just compile, to catch multilib mismatches.
+  # GCC 12+ separated _zicsr (CSR instructions) and _zifencei (fence.i)
+  # from the base "I" extension, requiring them to be listed explicitly in
+  # the -march string.  Detect with compile-only tests (-c).
+  #
+  # IMPORTANT: these extensions are added to CFLAGS only (compilation).
+  # They must NOT appear in LDFLAGS because GCC 15 decomposes the ISA
+  # string (m→zmmul, a→zaamo+zalrsc, c→zca) producing an expanded
+  # -march that has no matching multilib, causing a fatal error at
+  # link time.  The base march is multilib-safe for all GCC versions.
   RISCV32_ZICSR := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv32imac_zicsr -mabi=ilp32 -c -x c - -o /dev/null 2>/dev/null && echo _zicsr)
   RISCV32_ZIFENCEI := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv32imac_zifencei -mabi=ilp32 -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
-  ifneq ($(RISCV32_ZICSR)$(RISCV32_ZIFENCEI),)
-    # Link test using 64-bit integer division to force libgcc resolution.
-    # A trivial void _start(){} never references libgcc, hiding ABI
-    # mismatches (e.g., GCC 15 falling back to double-float libgcc).
-    RISCV32_EXT_LINK_OK := $(shell echo 'long long _d(long long a,long long b){return a/b;}void _start(void){_d(0,1);}' | \
-      $(CROSS_COMPILE)gcc -march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) \
-      -mabi=ilp32 -nostartfiles -x c - -o /dev/null 2>/dev/null && echo ok)
-    ifneq ($(RISCV32_EXT_LINK_OK),ok)
-      RISCV32_ZICSR :=
-      RISCV32_ZIFENCEI :=
-    endif
-  endif
-  ARCH_FLAGS=-march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) -mabi=ilp32 -mcmodel=medany
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV
-  CFLAGS+=$(ARCH_FLAGS)
-  LDFLAGS+=$(ARCH_FLAGS)
+  # Compilation: extended march so assembler accepts CSR/fence.i
+  CFLAGS+=-march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) -mabi=ilp32 -mcmodel=medany
+  # Linking: base march (no extension suffixes) for multilib lookup
+  LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
   MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c32.o
 
   # Prune unused functions and data
@@ -632,30 +626,22 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
-  # Detect zicsr/zifencei support with link verification (see RV32 comment)
+  # GCC 12+ extension detection (see RISCV 32-bit section above).
+  # Extensions go in CFLAGS only; LDFLAGS uses the base march to avoid
+  # GCC 15 multilib lookup failures from ISA string decomposition.
   RISCV64_ZICSR := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv64imafd_zicsr -mabi=lp64d -c -x c - -o /dev/null 2>/dev/null && echo _zicsr)
   RISCV64_ZIFENCEI := $(shell echo "void _start(void){}" | \
     $(CROSS_COMPILE)gcc -march=rv64imafd_zifencei -mabi=lp64d -c -x c - -o /dev/null 2>/dev/null && echo _zifencei)
-  ifneq ($(RISCV64_ZICSR)$(RISCV64_ZIFENCEI),)
-    # Link test using 128-bit integer division to force libgcc resolution.
-    # A trivial void _start(){} never references libgcc, hiding multilib
-    # mismatches (e.g., GCC 15 arch decomposition breaking multilib lookup).
-    RISCV64_EXT_LINK_OK := $(shell echo '__int128 _d(__int128 a,__int128 b){return a/b;}void _start(void){_d(0,1);}' | \
-      $(CROSS_COMPILE)gcc -march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) \
-      -mabi=lp64d -nostartfiles -x c - -o /dev/null 2>/dev/null && echo ok)
-    ifneq ($(RISCV64_EXT_LINK_OK),ok)
-      RISCV64_ZICSR :=
-      RISCV64_ZIFENCEI :=
-    endif
-  endif
 
   ifeq ($(RISCV_MMODE),1)
     # E51 core: rv64imac (no FPU, no crypto extensions)
-    ARCH_FLAGS=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
+    CFLAGS+=-march=rv64imac$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64 -mcmodel=medany
+    LDFLAGS+=-march=rv64imac -mabi=lp64 -mcmodel=medany
   else
     # U54 cores: rv64gc (with FPU)
-    ARCH_FLAGS=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
+    CFLAGS+=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
+    LDFLAGS+=-march=rv64imafd -mabi=lp64d -mcmodel=medany
 
     # FDT support for DDR S-mode (not needed for L2-LIM bare-metal boot)
     ifneq ($(MPFS_L2LIM),1)
@@ -664,8 +650,6 @@ ifeq ($(ARCH),RISCV64)
     endif
   endif
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV -DARCH_RISCV64
-  CFLAGS+=$(ARCH_FLAGS)
-  LDFLAGS+=$(ARCH_FLAGS)
 
   # Prune unused functions and data
   CFLAGS +=-ffunction-sections -fdata-sections

config/examples/polarfire_mpfs250_qspi.config

@@ -50,7 +50,6 @@ SPI_FLASH?=0
 #              on MSS QSPI pins.
 CFLAGS_EXTRA+=-DMPFS_SC_SPI
 
-
 # Enable SD card temporarily (wolfBoot still loads from SD, apps from QSPI)
 # For pure QSPI boot, HSS would need to load wolfBoot from QSPI
 DISK_SDCARD?=0
@@ -101,3 +100,10 @@ CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
 # Optional QSPI flash test (erase/write/read on update partition)
 # Uncomment to run test during hal_init()
 #CFLAGS_EXTRA+=-DTEST_EXT_FLASH
+
+# UART QSPI programmer (disabled by default)
+# When enabled, wolfBoot prompts on UART at startup to receive a signed firmware
+# image and write it to QSPI flash -- no Libero/JTAG tool required for updates.
+# Use: python3 tools/scripts/mpfs_qspi_prog.py <port> <image.bin> [qspi_offset]
+# Requires EXT_FLASH=1 (already set) and DEBUG_UART=1.
+UART_QSPI_PROGRAM?=0