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| 1 | +* Rockchip PX30 Clock and Reset Unit |
| 2 | + |
| 3 | +The PX30 clock controller generates and supplies clock to various |
| 4 | +controllers within the SoC and also implements a reset controller for SoC |
| 5 | +peripherals. |
| 6 | + |
| 7 | +Required Properties: |
| 8 | + |
| 9 | +- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" |
| 10 | +- compatible: CRU should be "rockchip,px30-cru" |
| 11 | +- reg: physical base address of the controller and length of memory mapped |
| 12 | + region. |
| 13 | +- #clock-cells: should be 1. |
| 14 | +- #reset-cells: should be 1. |
| 15 | + |
| 16 | +Optional Properties: |
| 17 | + |
| 18 | +- rockchip,grf: phandle to the syscon managing the "general register files" |
| 19 | + If missing, pll rates are not changeable, due to the missing pll lock status. |
| 20 | + |
| 21 | +Each clock is assigned an identifier and client nodes can use this identifier |
| 22 | +to specify the clock which they consume. All available clocks are defined as |
| 23 | +preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be |
| 24 | +used in device tree sources. Similar macros exist for the reset sources in |
| 25 | +these files. |
| 26 | + |
| 27 | +External clocks: |
| 28 | + |
| 29 | +There are several clocks that are generated outside the SoC. It is expected |
| 30 | +that they are defined using standard clock bindings with following |
| 31 | +clock-output-names: |
| 32 | + - "xin24m" - crystal input - required, |
| 33 | + - "xin32k" - rtc clock - optional, |
| 34 | + - "i2sx_clkin" - external I2S clock - optional, |
| 35 | + - "gmac_clkin" - external GMAC clock - optional |
| 36 | + |
| 37 | +Example: Clock controller node: |
| 38 | + |
| 39 | + pmucru: pmu-clock-controller@ff2bc000 { |
| 40 | + compatible = "rockchip,px30-pmucru"; |
| 41 | + reg = <0x0 0xff2bc000 0x0 0x1000>; |
| 42 | + #clock-cells = <1>; |
| 43 | + #reset-cells = <1>; |
| 44 | + }; |
| 45 | + |
| 46 | + cru: clock-controller@ff2b0000 { |
| 47 | + compatible = "rockchip,px30-cru"; |
| 48 | + reg = <0x0 0xff2b0000 0x0 0x1000>; |
| 49 | + rockchip,grf = <&grf>; |
| 50 | + #clock-cells = <1>; |
| 51 | + #reset-cells = <1>; |
| 52 | + }; |
| 53 | + |
| 54 | +Example: UART controller node that consumes the clock generated by the clock |
| 55 | + controller: |
| 56 | + |
| 57 | + uart0: serial@ff030000 { |
| 58 | + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; |
| 59 | + reg = <0x0 0xff030000 0x0 0x100>; |
| 60 | + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 61 | + clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; |
| 62 | + clock-names = "baudclk", "apb_pclk"; |
| 63 | + reg-shift = <2>; |
| 64 | + reg-io-width = <4>; |
| 65 | + status = "disabled"; |
| 66 | + }; |
| 67 | + |
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